Gokhan Memik

According to our database1, Gokhan Memik authored at least 123 papers between 2000 and 2022.

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Bibliography

2022
Physical activity forecasting with time series data using Android smartphone.
Pervasive Mob. Comput., 2022

2020
DeepSwapper: A Deep Learning Based Page Swap Management Scheme for Hybrid Memory Systems.
Proceedings of the PACT '20: International Conference on Parallel Architectures and Compilation Techniques, 2020

2019
Writeback-Aware LLC Management for PCM-Based Main Memory Systems.
ACM Trans. Design Autom. Electr. Syst., 2019

Using Built-In Sensors to Predict and Utilize User Satisfaction for CPU Settings on Smartphones.
Proc. ACM Interact. Mob. Wearable Ubiquitous Technol., 2019

Understanding the impact of number of CPU cores on user satisfaction in smartphones.
Proceedings of the MobiQuitous 2019, 2019

2018
Machine Learning-Based Temperature Prediction for Runtime Thermal Management Across System Components.
IEEE Trans. Parallel Distributed Syst., 2018

THOR: THermal-aware Optimizations for extending ReRAM Lifetime.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium, 2018

Minimizing Thermal Variation in Heterogeneous HPC Systems with FPGA Nodes.
Proceedings of the 36th IEEE International Conference on Computer Design, 2018

WALL: A writeback-aware LLC management for PCM-based main memory systems.
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Thermal-aware optimizations of reRAM-based neuromorphic computing systems.
Proceedings of the 55th Annual Design Automation Conference, 2018

2017
User-aware Frame Rate Management in Android Smartphones.
ACM Trans. Embed. Comput. Syst., 2017

UStress: Understanding college student subjective stress using wrist-based passive sensing.
Proceedings of the 2017 IEEE International Conference on Pervasive Computing and Communications Workshops, 2017

Evaluating irregular memory access on OpenCL FPGA platforms: A case study with XSBench.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

2016
TAPAS: Temperature-aware Adaptive Placement for 3D Stacked Hybrid Caches.
Proceedings of the Second International Symposium on Memory Systems, 2016

Therma: Thermal-aware Run-time Thread Migration for Nanophotonic Interconnects.
Proceedings of the 2016 International Symposium on Low Power Electronics and Design, 2016

Analyzing power consumption and characterizing user activities on smartwatches: summary.
Proceedings of the 2016 IEEE International Symposium on Workload Characterization, 2016

TESLA: Using microfluidics to thermally stabilize 3D stacked STT-RAM caches.
Proceedings of the 34th IEEE International Conference on Computer Design, 2016

2015
Emitter-Coupled Spin-Transistor Logic: Cascaded Spintronic Computing Beyond 10 GHz.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2015

Minimizing Thermal Variation Across System Components.
Proceedings of the 2015 IEEE International Parallel and Distributed Processing Symposium, 2015

SCP: Synergistic cache compression and prefetching.
Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

User-specific skin temperature-aware DVFS for smartphones.
Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Optimizing mobile display brightness by leveraging human visual perception.
Proceedings of the 2015 International Conference on Compilers, 2015

2014
Emitter-coupled spin-transistor logic.
J. Parallel Distributed Comput., 2014

MIN: a power efficient mechanism to mitigate the impact of process variations on nanophotonic networks.
Proceedings of the International Symposium on Low Power Electronics and Design, 2014

Galaxy: a high-performance energy-efficient multi-chip architecture using photonic interconnects.
Proceedings of the 2014 International Conference on Supercomputing, 2014

CAPED: Context-aware personalized display brightness for mobile devices.
Proceedings of the 2014 International Conference on Compilers, 2014

2013
HAPPE: Human and Application-Driven Frequency Scaling for Processor Power Efficiency.
IEEE Trans. Mob. Comput., 2013

The Impact of Dynamic Directories on Multicore Interconnects.
Computer, 2013

2012
Fine-Grain Voltage Tuned Cache Architecture for Yield Management Under Process Variations.
IEEE Trans. Very Large Scale Integr. Syst., 2012

Emitter-coupled spin-transistor logic.
Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

Understanding the impact of laptop power saving options on user satisfaction using physiological sensors.
Proceedings of the International Symposium on Low Power Electronics and Design, 2012

Dynamic Directories: A mechanism for reducing on-chip interconnect power in multicores.
Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

2011
Accelerating data mining workloads: current approaches and future challenges in system architecture design.
WIREs Data Mining Knowl. Discov., 2011

Demo: indoor localization without infrastructure using the acoustic background spectrum.
Proceedings of the 9th International Conference on Mobile Systems, 2011

Indoor localization without infrastructure using the acoustic background spectrum.
Proceedings of the 9th International Conference on Mobile Systems, 2011

FeatherWeight: low-cost optical arbitration with QoS support.
Proceedings of the 44rd Annual IEEE/ACM International Symposium on Microarchitecture, 2011

High Performance Data Mining Using R on Heterogeneous Platforms.
Proceedings of the 25th IEEE International Symposium on Parallel and Distributed Processing, 2011

Hardware/software techniques for DRAM thermal management.
Proceedings of the 17th International Conference on High-Performance Computer Architecture (HPCA-17 2011), 2011

2010
An Approach for Adaptive DRAM Temperature and Power Management.
IEEE Trans. Very Large Scale Integr. Syst., 2010

User identification based on finger-vein patterns for consumer electronics devices.
IEEE Trans. Consumer Electron., 2010

Characterizing and modeling user activity on smartphones: summary.
Proceedings of the SIGMETRICS 2010, 2010

Display power management policies in practice.
Proceedings of the 7th International Conference on Autonomic Computing, 2010

FlexiShare: Channel sharing for an energy-efficient nanophotonic crossbar.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

Detecting/preventing information leakage on the memory bus due to malicious hardware.
Proceedings of the Design, Automation and Test in Europe, 2010

Quantifying and coping with parametric variations in 3D-stacked microarchitectures.
Proceedings of the 47th Design Automation Conference, 2010

2009
Exploring concentration and channel slicing in on-chip network router.
Proceedings of the Third International Symposium on Networks-on-Chips, 2009

Into the wild: studying real user activity patterns to guide power optimizations for mobile architectures.
Proceedings of the 42st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-42 2009), 2009

Analyzing the impact of on-chip network traffic on program phases for CMPs.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

User- and process-driven dynamic voltage and frequency scaling.
Proceedings of the IEEE International Symposium on Performance Analysis of Systems and Software, 2009

Firefly: illuminating future network-on-chip with nanophotonics.
Proceedings of the 36th International Symposium on Computer Architecture (ISCA 2009), 2009

Sonar-based measurement of user presence and attention.
Proceedings of the UbiComp 2009: Ubiquitous Computing, 2009

Selective wordline voltage boosting for caches to manage yield under process variations.
Proceedings of the 46th Design Automation Conference, 2009

2008
An FPGA-Based Network Intrusion Detection Architecture.
IEEE Trans. Inf. Forensics Secur., 2008

Thermal monitoring mechanisms for chip multiprocessors.
ACM Trans. Archit. Code Optim., 2008

Energy Detection Using Estimated Noise Variance for Spectrum Sensing in Cognitive Radio Networks.
Proceedings of the WCNC 2008, IEEE Wireless Communications & Networking Conference, March 31 2008, 2008

Power to the people: Leveraging human physiological traits to control microprocessor frequency.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Evaluating the effects of cache redundancy on profit.
Proceedings of the 41st Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-41 2008), 2008

Learning and Leveraging the Relationship between Architecture-Level Measurements and Individual User Satisfaction.
Proceedings of the 35th International Symposium on Computer Architecture (ISCA 2008), 2008

Machine Learning Models to Predict Performance of Computer System Design Alternatives.
Proceedings of the 2008 International Conference on Parallel Processing, 2008

Towards an "early neural circuit simulator": A FPGA implementation of processing in the rat whisker system.
Proceedings of the FPL 2008, 2008

An Efficient FPGA Implementation of Principle Component Analysis based Network Intrusion Detection System.
Proceedings of the Design, Automation and Test in Europe, 2008

Efficient system design space exploration using machine learning techniques.
Proceedings of the 45th Design Automation Conference, 2008

A power and temperature aware DRAM architecture.
Proceedings of the 45th Design Automation Conference, 2008

Archer: A Community Distributed Computing Infrastructure for Computer Architecture Research and Education.
Proceedings of the Collaborative Computing: Networking, 2008

PICSEL: measuring user-perceived performance to control dynamic frequency scaling.
Proceedings of the 13th International Conference on Architectural Support for Programming Languages and Operating Systems, 2008

2007
Thermal Management of On-Chip Caches Through Power Density Minimization.
IEEE Trans. Very Large Scale Integr. Syst., 2007

Reversible sketches: enabling monitoring and analysis over high-speed data streams.
IEEE/ACM Trans. Netw., 2007

Microarchitectures for Managing Chip Revenues under Process Variations.
IEEE Comput. Archit. Lett., 2007

Spectrum Sensing Using Cyclostationary Spectrum Density for Cognitive Radios.
Proceedings of the IEEE Workshop on Signal Processing Systems, 2007

Power reduction through measurement and modeling of users and CPUs: summary.
Proceedings of the 2007 ACM SIGMETRICS International Conference on Measurement and Modeling of Computer Systems, 2007

Variable latency caches for nanoscale processor.
Proceedings of the ACM/IEEE Conference on High Performance Networking and Computing, 2007

Digital Modulation Classification using Temporal Waveform Features for Cognitive Radios.
Proceedings of the IEEE 18th International Symposium on Personal, 2007

Evaluating voltage islands in CMPs under process variations.
Proceedings of the 25th International Conference on Computer Design, 2007

Quantization Error and Accuracy-Performance Tradeoffs for Embedded Data Mining Workloads.
Proceedings of the Computational Science - ICCS 2007, 7th International Conference, Beijing, China, May 27, 2007

Design and Implementation of an FPGA Architecture for High-Speed Network Feature Extraction.
Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

The user in experimental computer systems research.
Proceedings of the Workshop on Experimental Computer Science, 2007

Interactive presentation: An FPGA based all-digital transmitter with radio frequency output for software defined radio.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Interactive presentation: An FPGA implementation of decision tree classification.
Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Automated task distribution in multicore network processors using statistical analysis.
Proceedings of the 2007 ACM/IEEE Symposium on Architecture for Networking and Communications Systems, 2007

2006
Multicollective I/O: A technique for exploiting inter-file access patterns.
ACM Trans. Storage, 2006

Evaluating Network Processors using NetBench.
ACM Trans. Embed. Comput. Syst., 2006

User-Driven Frequency Scaling.
IEEE Comput. Archit. Lett., 2006

Yield-Aware Cache Architectures.
Proceedings of the 39th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-39 2006), 2006

Reverse Hashing for High-Speed Network Monitoring: Algorithms, Evaluation, and Applications.
Proceedings of the INFOCOM 2006. 25th IEEE International Conference on Computer Communications, 2006

An Architectural Characterization Study of Data Mining and Bioinformatics Workloads.
Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

MineBench: A Benchmark Suite for Data Mining Workloads.
Proceedings of the 2006 IEEE International Symposium on Workload Characterization, 2006

Power density minimization for highly-associative caches in embedded processors.
Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

A reconfigurable architecture for network intrusion detection using principal component analysis.
Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

2005
Low Power Correlating Caches for Network Processors.
J. Low Power Electron., 2005

Precise Instruction Scheduling.
J. Instr. Level Parallelism, 2005

Application-Level Error Measurements for Network Processors.
IEICE Trans. Inf. Syst., 2005

Peak temperature control and leakage reduction during binding in high level synthesis.
Proceedings of the 2005 International Symposium on Low Power Electronics and Design, 2005

Tornado warning: the perils of selective replay in multithreaded processors.
Proceedings of the 19th Annual International Conference on Supercomputing, 2005

Reducing the Energy of Speculative Instruction Schedulers.
Proceedings of the 23rd International Conference on Computer Design (ICCD 2005), 2005

Load elimination for low-power embedded processors.
Proceedings of the 15th ACM Great Lakes Symposium on VLSI 2005, 2005

Real-Time Feature Extraction for High Speed Networks.
Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Engineering Over-Clocking: Reliability-Performance Trade-Offs for High-Performance Register Files.
Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005

Increasing Register File Immunity to Transient Errors.
Proceedings of the 2005 Design, 2005

Temperature-aware resource allocation and binding in high-level synthesis.
Proceedings of the 42nd Design Automation Conference, 2005

Automatic extraction of function bodies from software binaries.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Compiler-directed selective data protection against soft errors.
Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

2004
A Case for Clumsy Packet Processors.
Proceedings of the 37th Annual International Symposium on Microarchitecture (MICRO-37 2004), 2004

Design and implementation of correlating caches.
Proceedings of the 2004 International Symposium on Low Power Electronics and Design, 2004

Scaling the issue window with look-ahead latency prediction.
Proceedings of the 18th Annual International Conference on Supercomputing, 2004

Flow Monitoring in High-Speed Networks with 2D Hash Tables.
Proceedings of the Field Programmable Logic and Application, 2004

2003
A high-performance application data environment for large-scale scientific computations.
IEEE Trans. Parallel Distributed Syst., 2003

Reducing energy and delay using efficient victim caches.
Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Just Say No: Benefits of Early Cache Miss Determinatio.
Proceedings of the Ninth International Symposium on High-Performance Computer Architecture (HPCA'03), 2003

An Integrated Approach for Improving Cache Behavior.
Proceedings of the 2003 Design, 2003

Global resource sharing for synthesis of control data flow graphs on FPGAs.
Proceedings of the 40th Design Automation Conference, 2003

Hardware/Software Techniques for Improving Cache Performance in Embedded Systems.
Proceedings of the Embedded Software for SoC, 2003

2002
Design and Analysis of a Layer Seven Network Processor Accelerator Using Reconfigurable Logic.
Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

Exploiting Inter-File Access Patterns Using Multi-Collective I/O.
Proceedings of the FAST '02 Conference on File and Storage Technologies, 2002

A flexible accelerator for layer 7 networking applications.
Proceedings of the 39th Design Automation Conference, 2002

Increasing power efficiency of multi-core network processors through data filtering.
Proceedings of the International Conference on Compilers, 2002

2001
Design and Evaluation of a Smart Disk Cluster for DSS Commercial Workloads.
J. Parallel Distributed Comput., 2001

NetBench: A Benchmarking Suite for Network Processors.
Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

JETTY: Filtering Snoops for Reduced Energy Consumption in SMP Servers.
Proceedings of the Seventh International Symposium on High-Performance Computer Architecture (HPCA'01), 2001

2000
Data management for large-scale scientific computations in high performance distributed systems.
Clust. Comput., 2000

APRIL: A Run-Time Library for Tape-Resident Data.
Proceedings of the Eighth NASA Goddard Space Flight Center Conference on Mass Storage Systems and Technologies in cooperation with Seventeenth IEEE Symposium on Mass Storage Systems, 2000

A novel application development environment for large-scale scientific computations.
Proceedings of the 14th international conference on Supercomputing, 2000

Design and Evaluation of Smart Disk Architecture for DSS Commercial Workloads.
Proceedings of the 2000 International Conference on Parallel Processing, 2000

Design and Evaluation of a Compiler-Directed Collective I/O Technique.
Proceedings of the Euro-Par 2000, Parallel Processing, 6th International Euro-Par Conference, Munich, Germany, August 29, 2000


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