Giuseppe Tagliavini
Orcid: 0000-0002-9221-4633
According to our database1,
Giuseppe Tagliavini
authored at least 63 papers
between 2011 and 2024.
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Bibliography
2024
Balancing Accuracy and Energy Efficiency on Ultra-Law-Power Platforms for ECG Analysis.
Proceedings of the IEEE International Conference on Omni-layer Intelligent Systems, 2024
SeTHet - Sending Tuned numbers over DMA onto Heterogeneous clusters: an automated precision tuning story.
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024
QR-PULP: Streamlining QR Decomposition for RISC-V Parallel Ultra-Low-Power Platforms.
Proceedings of the 21st ACM International Conference on Computing Frontiers, 2024
2023
IEEE Trans. Very Large Scale Integr. Syst., April, 2023
DNN Is Not All You Need: Parallelizing Non-neural ML Algorithms on Ultra-low-power IoT Processors.
ACM Trans. Embed. Comput. Syst., 2023
Dustin: A 16-Cores Parallel Ultra-Low-Power Cluster With 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode.
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
CoRR, 2023
Proceedings of the 9th International Workshop on Advances in Sensors and Interfaces, 2023
Optimizing Self-Organizing Maps for Bacterial Genome Identification on Parallel Ultra-Low-Power Platforms.
Proceedings of the 30th IEEE International Conference on Electronics, Circuits and Systems, 2023
RUST-Encoded Stream Ciphers on a RISC-V Parallel Ultra-Low-Power Processor (Invited Paper).
Proceedings of the 14th Workshop on Parallel Programming and Run-Time Management Techniques for Many-Core Architectures and 12th Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2023
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
TransLib: A Library to Explore Transprecision Floating-Point Arithmetic on Multi-Core IoT End-Nodes.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
End-to-End DNN Inference on a Massively Parallel Analog In Memory Computing Architecture.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023
2022
A Low-Power Transprecision Floating-Point Cluster for Efficient Near-Sensor Data Analytics.
IEEE Trans. Parallel Distributed Syst., 2022
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022
Vega: A Ten-Core SoC for IoT Endnodes With DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
IEEE J. Solid State Circuits, 2022
An Optimized Heart Rate Detection System Based on Low-Power Microcontroller Platforms for Biosignal Processing.
Proceedings of the Advances in System-Integrated Intelligence, 2022
PULP-TrainLib: Enabling On-Device Training for RISC-V Multi-core MCUs Through Performance-Driven Autotuning.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2022
Scale up your In-Memory Accelerator: Leveraging Wireless-on-Chip Communication for AIMC-based CNN Inference.
Proceedings of the 4th IEEE International Conference on Artificial Intelligence Circuits and Systems, 2022
2021
Energy-Efficient Hardware-Accelerated Synchronization for Shared-L1-Memory Multiprocessor Clusters.
IEEE Trans. Parallel Distributed Syst., 2021
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Networks on RISC-V Based IoT End Nodes.
IEEE Trans. Emerg. Top. Comput., 2021
IEEE Trans. Computers, 2021
IEEE Embed. Syst. Lett., 2021
Vega: A 10-Core SoC for IoT End-Nodes with DNN Acceleration and Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
CoRR, 2021
RVfplib: A Fast and Compact Open-Source Floating-Point Emulation Library for Tiny RISC-V Processors.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2021
4.4 A 1.3TOPS/W @ 32GOPS Fully Integrated 10-Core SoC for IoT End-Nodes with 1.7μW Cognitive Wake-Up From MRAM-Based State-Retentive Sleep Mode.
Proceedings of the IEEE International Solid-State Circuits Conference, 2021
GVSoC: A Highly Configurable, Fast and Accurate Full-Platform Simulator for RISC-V based IoT Processors.
Proceedings of the 39th IEEE International Conference on Computer Design, 2021
A 1.15 TOPS/W, 16-Cores Parallel Ultra-Low Power Cluster with 2b-to-32b Fully Flexible Bit-Precision and Vector Lockstep Execution Mode.
Proceedings of the 47th ESSCIRC 2021, 2021
Source Code Classification for Energy Efficiency in Parallel Ultra Low-Power Microcontrollers.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021
Proceedings of the IEEE Biomedical Circuits and Systems Conference, BioCAS 2021, 2021
Proceedings of the Architecture of Computing Systems - 34th International Conference, 2021
2020
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020
XpulpNN: Enabling Energy Efficient and Flexible Inference of Quantized Neural Network on RISC-V based IoT End Nodes.
CoRR, 2020
CoRR, 2020
Proceedings of the 2020 IEEE Computer Society Annual Symposium on VLSI, 2020
TRANSPIRE: An energy-efficient TRANSprecision floating-point Programmable archItectuRE.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
XpulpNN: Accelerating Quantized Neural Networks on RISC-V Processors Through ISA Extensions.
Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020
Proceedings of the 17th ACM International Conference on Computing Frontiers, 2020
2019
BioWolf: A Sub-10-mW 8-Channel Advanced Brain-Computer Interface Platform With a Nine-Core Processor and BLE Connectivity.
IEEE Trans. Biomed. Circuits Syst., 2019
Mr.Wolf: An Energy-Precision Scalable Parallel Ultra Low Power SoC for IoT Edge Processing.
IEEE J. Solid State Circuits, 2019
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019
2018
Unleashing Fine-Grained Parallelism on Embedded Many-Core Accelerators with Lightweight OpenMP Tasking.
IEEE Trans. Parallel Distributed Syst., 2018
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018
Optimizing memory bandwidth exploitation for OpenVX applications on embedded many-core accelerators.
J. Real Time Image Process., 2018
A Transprecision Floating-Point Architecture for Energy-Efficient Embedded Computing.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018
2017
Optimization Techniques for Parallel Programming of Embedded Many-Core Computing Platforms.
PhD thesis, 2017
2016
Always-on motion detection with application-level error control on a near-threshold approximate computing platform.
Proceedings of the 2016 IEEE International Conference on Electronics, Circuits and Systems, 2016
Proceedings of the 2016 International Conference on Compilers, 2016
2015
IEEE Trans. Ind. Informatics, 2015
A framework for optimizing OpenVX applications performance on embedded manycore accelerators.
Proceedings of the 18th International Workshop on Software and Compilers for Embedded Systems, 2015
ADRENALINE: An OpenVX Environment to Optimize Embedded Vision Applications on Many-core Accelerators.
Proceedings of the IEEE 9th International Symposium on Embedded Multicore/Many-core Systems-on-Chip, 2015
Synergistic Architecture and Programming Model Support for Approximate Micropower Computing.
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
Proceedings of the 21st IEEE International Symposium on High Performance Computer Architecture, 2015
Proceedings of the 2015 IEEE Hot Chips 27 Symposium (HCS), 2015
2014
Tightly-coupled hardware support to dynamic parallelism acceleration in embedded shared memory clusters.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014
Optimizing memory bandwidth in OpenVX graph execution on embedded many-core accelerators.
Proceedings of the 2014 Conference on Design and Architectures for Signal and Image Processing, 2014
Supporting localized OpenVX kernel execution for efficient computer vision application development on STHORM many-core platform.
Proceedings of the Computing Frontiers Conference, CF'14, 2014
2013
Improving the programmability of STHORM-based heterogeneous systems with offload-enabled OpenMP.
Proceedings of the 1st International Workshop on Many-core Embedded Systems 2013, 2013
Proceedings of the Design, Automation and Test in Europe, 2013
2011
MPOpt-Cell: a high-performance data-flow programming environment for the CELL BE processor.
Proceedings of the 8th Conference on Computing Frontiers, 2011