Giuseppe Surace
According to our database1,
Giuseppe Surace
authored at least 7 papers
between 2011 and 2022.
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Collaborative distances:
Timeline
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2022
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2022
Federated Learning for the Efficient Detection of Steganographic Threats Hidden in Image Icons.
Proceedings of the Pervasive Knowledge and Collective Intelligence on Web and Social Media, 2022
2020
IEEE J. Solid State Circuits, 2020
Proceedings of the 2020 IEEE Custom Integrated Circuits Conference, 2020
2019
Proceedings of the 2019 Symposium on VLSI Circuits, Kyoto, Japan, June 9-14, 2019, 2019
2016
10.1 A pin-efficient 20.83Gb/s/wire 0.94pJ/bit forwarded clock CNRZ-5-coded SerDes up to 12mm for MCM packages in 28nm CMOS.
Proceedings of the 2016 IEEE International Solid-State Circuits Conference, 2016
2014
26.3 A pin- and power-efficient low-latency 8-to-12Gb/s/wire 8b8w-coded SerDes link for high-loss channels in 40nm technology.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014
2011
Analog-DFE-based 16Gb/s SerDes in 40nm CMOS that operates across 34dB loss channels at Nyquist with a baud rate CDR and 1.2Vpp voltage-mode driver.
Proceedings of the IEEE International Solid-State Circuits Conference, 2011