Giuseppe Natale

According to our database1, Giuseppe Natale authored at least 14 papers between 2016 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
On the Computation of 2-Dimensional Recurrence Equations.
CoRR, 2024

2021
Enhancing the Scalability of Multi-FPGA Stencil Computations via Highly Optimized HDL Components.
ACM Trans. Reconfigurable Technol. Syst., 2021

2020
Enabling transparent hardware acceleration on Zynq SoC for scientific computing.
SIGBED Rev., 2020

2019
On how to design optimized spatial architectures: from iterative stencils to convolutional neural networks.
PhD thesis, 2019

2018
An FPGA-Based Acceleration Methodology and Performance Model for Iterative Stencils.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

A Framework with Cloud Integration for CNN Acceleration on FPGA Devices.
Proceedings of the 2018 IEEE International Parallel and Distributed Processing Symposium Workshops, 2018

2017
A CAD Open Platform for High Performance Reconfigurable Systems in the EXTRA Project.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

On How to Design Dataflow FPGA-Based Accelerators for Convolutional Neural Networks.
Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

A Pipelined and Scalable Dataflow Implementation of Convolutional Neural Networks on FPGA.
Proceedings of the 2017 IEEE International Parallel and Distributed Processing Symposium Workshops, 2017

Optimizing streaming stencil time-step designs via FPGA floorplanning.
Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

A Feedback-Based Design Space Exploration Subsystem for the Automation of Architectures Synthesis on Proprietary FPGA Toolchains.
Proceedings of the Euromicro Conference on Digital System Design, 2017

Heterogeneous exascale supercomputing: The role of CAD in the exaFPGA project.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

2016
On How to Accelerate Iterative Stencil Loops: A Scalable Streaming-Based Approach.
ACM Trans. Archit. Code Optim., 2016

A polyhedral model-based framework for dataflow implementation on FPGA devices of iterative stencil loops.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016


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