Giuseppe Gramegna

According to our database1, Giuseppe Gramegna authored at least 9 papers between 2001 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

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In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
A D-band Power-Combined Stacked Common-Base Power Amplifier Achieving 20.9 dBm Psat and 24.3 % PAE in a 250-nm InP HBT Technology.
Proceedings of the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium, 2024

2022
(Why do we need) Wireless Heterogeneous Integration (anyway?).
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

2021
A Low-Power Reflection-Coefficient Sensor for 28-GHz Beamforming Transmitters in 22-nm FD-SOI CMOS.
IEEE J. Solid State Circuits, 2021

InP / CMOS co-integration for energy efficient sub-THz communication systems.
Proceedings of the IEEE Globecom 2021 Workshops, Madrid, Spain, December 7-11, 2021, 2021

2018
Session 26 overview: RF techniques for communication and sensing: RF subcommittee.
Proceedings of the 2018 IEEE International Solid-State Circuits Conference, 2018

2006
A 56-mW 23-mm<sup>2</sup> single-chip 180-nm CMOS GPS receiver with 27.2-mW 4.1-mm<sup>2</sup> radio.
IEEE J. Solid State Circuits, 2006

2004
23mm<sup>2</sup> single-chip 0.18μm CMOS GPS receiver with 28mW-4.1 mm<sup>2</sup> radio and CPU/DSP/RAM/ROM.
Proceedings of the IEEE 2004 Custom Integrated Circuits Conference, 2004

2003
A 35-mW 3.6-mm2 fully integrated 0.18-μm CMOS GPS radio.
IEEE J. Solid State Circuits, 2003

2001
A sub-1-dB NF±2.3-kV ESD-protected 900-MHz CMOS LNA.
IEEE J. Solid State Circuits, 2001


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