Girish Pahwa

According to our database, Girish Pahwa authored at least 17 papers between 2016 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

Technology Mapping for Cryogenic CMOS Circuits.

Benjamin Hien, Marcel Walter, Victor M. van Santen, Florian Klemme, Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch, Robert Wille

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2024

Impact of Self-Heating in 5nm FinFETs at Cryogenic Temperatures for Reliable Quantum Computing: Device-Circuit Interaction.

Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch

Proceedings of the IEEE International Reliability Physics Symposium, 2024

2023

FerroX: A GPU-accelerated, 3D phase-field simulation framework for modeling ferroelectric devices.

Prabhat Kumar, Andrew Nonaka, Revathi Jambunathan, Girish Pahwa, Sayeef S. Salahuddin, Zhi Yao

Comput. Phys. Commun., September, 2023

Cryogenic CMOS for Quantum Processing: 5-nm FinFET-Based SRAM Arrays at 10 K.

Shivendra Singh Parihar, Victor M. van Santen, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch

IEEE Trans. Circuits Syst. I Regul. Pap., 2023

Robust Compact Model of High-Voltage MOSFET's Drift Region.

Girish Pahwa, Ayushi Sharma, Ravi Goel, Garima Gill, Harshit Agarwal, Yogesh Singh Chauhan, Chenming Hu

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2023

Cryogenic In-Memory Computing for Quantum Processors Using Commercial 5-nm FinFETs.

Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch

IEEE Open J. Circuits Syst., 2023

5nm FinFET Cryogenic SRAM Evaluation for Quantum Computing.

Shivendra Singh Parihar, Simon Thomann, Girish Pahwa, Yogesh Singh Chauhan, Hussam Amrouch

Proceedings of the Device Research Conference, 2023

Design Automation for Cryogenic CMOS Circuits.

Victor M. van Santen, Marcel Walter, Florian Klemme, Shivendra Singh Parihar, Girish Pahwa, Yogesh Singh Chauhan, Robert Wille, Hussam Amrouch

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

2022

Compact Model for Trap Assisted Tunneling based GIDL.

Chetan K. Dabhi, Girish Pahwa, Sayeef S. Salahuddin, Chenming Hu

Proceedings of the Device Research Conference, 2022

2021

On the Resiliency of NCFET Circuits Against Voltage Over-Scaling.

Guilherme Paim, Georgios Zervakis, Girish Pahwa, Yogesh Singh Chauhan, Eduardo Antonio Cesar da Costa, Sergio Bampi, Jörg Henkel, Hussam Amrouch

IEEE Trans. Circuits Syst. I Regul. Pap., 2021

2020

Impact of Variability on Processor Performance in Negative Capacitance FinFET Technology.

Hussam Amrouch, Girish Pahwa, Amol D. Gaidhane, Chetan K. Dabhi, Florian Klemme, Om Prakash, Yogesh Singh Chauhan

IEEE Trans. Circuits Syst. I Regul. Pap., 2020

Impact of Radiation on Negative Capacitance FinFET.

Govind Bajpai, Aniket Gupta, Om Prakash, Girish Pahwa, Jörg Henkel, Yogesh Singh Chauhan, Hussam Amrouch

Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020

NCFET to Rescue Technology Scaling: Opportunities and Challenges.

Hussam Amrouch, Victor M. van Santen, Girish Pahwa, Yogesh Singh Chauhan, Jörg Henkel

Proceedings of the 25th Asia and South Pacific Design Automation Conference, 2020

2019

NCFET-Aware Voltage Scaling.

Sami Salamin, Martin Rapp, Hussam Amrouch, Girish Pahwa, Yogesh Singh Chauhan, Jörg Henkel

Proceedings of the 2019 IEEE/ACM International Symposium on Low Power Electronics and Design, 2019

Performance, Power and Cooling Trade-Offs with NCFET-based Many-Cores.

Martin Rapp, Sami Salamin, Hussam Amrouch, Girish Pahwa, Yogesh Singh Chauhan, Jörg Henkel

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

2018

Negative Capacitance Transistor to Address the Fundamental Limitations in Technology Scaling: Processor Performance.

Hussam Amrouch, Girish Pahwa, Amol D. Gaidhane, Jörg Henkel, Yogesh Singh Chauhan

IEEE Access, 2018

2016

Designing energy efficient and hysteresis free negative capacitance FinFET with negative DIBL and 3.5X ION using compact modeling approach.

Girish Pahwa, Tapas Dutta, Amit Agarwal, Yogesh Singh Chauhan

Proceedings of the ESSCIRC Conference 2016: 42^nd European Solid-State Circuits Conference, 2016