Giovanni Staino

According to our database1, Giovanni Staino authored at least 8 papers between 2001 and 2009.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2009
Quad-Port Memory Blocks in Radiation-Tolerant FPGAs: An Application for Image Processing Systems.
Proceedings of the Second International Conference on Emerging Trends in Engineering & Technology, 2009

2007
Design and Implementation of a 90nm Low bit-rate Image Compression Core.
Proceedings of the Tenth Euromicro Conference on Digital System Design: Architectures, 2007

2006
Low bit rate image compression core for onboard space applications.
IEEE Trans. Circuits Syst. Video Technol., 2006

2003
CARMEN: cellular automata reconfigurable machine for effective computation.
PhD thesis, 2003

A low-power sub-nanosecond standard-cells based adder.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

2002
Efficient Implementation of Cellular Algorithms on Reconfigurable Hardware.
Proceedings of the 10th Euromicro Workshop on Parallel, 2002

2001
VLSI implementation of a fully static CMOS 56-bit self-timed adder using overlapped execution circuits.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Dynamic power of CMOS gates driving lossy transmission lines.
Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001


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