Giovanni De Micheli

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., May, 2024

Expediting Homomorphic Computation via Multiplicative Complexity-aware Multiplicative Depth Minimization.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2024

Practical Boolean Decomposition for Delay-driven LUT Mapping.

[BibT_eX]

[DOI]

Alan Mishchenko

CoRR, 2024

Quantum State Preparation Using an Exact CNOT Synthesis Formulation.

[BibT_eX]

[DOI]

CoRR, 2024

On the Synthesis of High-performance Homomorphic Boolean Circuits.

[BibT_eX]

[DOI]

Sergiu Carpov

Proceedings of the 12th Workshop on Encrypted Computing & Applied Homomorphic Cryptography, 2024

An Enhanced Resubstitution Algorithm for Area-Oriented Logic Optimization.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2024

Quantum State Preparation Using an Exact CNOT Synthesis Formulation.

[BibT_eX]

[DOI]

Hanyu Wang

Jason Cong

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

VACSEM: Verifying Average Errors in Approximate Circuits Using Simulation-Enhanced Model Counting.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Scalable Sequential Optimization Under Observability Don't Cares.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Scalable Logic Rewriting Using Don't Cares.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Technology-Aware Logic Synthesis for Superconducting Electronics.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Late Breaking Results: Majority-Inverter Graph Minimization by Design Space Exploration.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

Unleashing the Power of T1-cells in SFQ Arithmetic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 61st ACM/IEEE Design Automation Conference, 2024

In Medio Stat Virtus*: Combining Boolean and Pattern Matching.

[BibT_eX]

[DOI]

Gianluca Radi

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

Algebraic and Boolean Methods for SFQ Superconducting Circuits.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

Towards Multiphase Clocking in Single-Flux Quantum Systems.

[BibT_eX]

[DOI]

Proceedings of the 29th Asia and South Pacific Design Automation Conference, 2024

2023

Heuristic Logic Resynthesis Algorithms at the Core of Peephole Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., November, 2023

Strange Loops in Design and Technology: 59th DAC Keynote Speech.

[BibT_eX]

[DOI]

IEEE Des. Test, October, 2023

Garbled Circuits Reimagined: Logic Synthesis Unleashes Efficient Secure Computation.

[BibT_eX]

[DOI]

Cryptogr., September, 2023

Utilizing XMG-Based Synthesis to Preserve Self-Duality for RFET-Based Circuits.

[BibT_eX]

[DOI]

Shubham Rai

Akash Kumar

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., March, 2023

Accuracy recovery: A decomposition procedure for the synthesis of partially-specified Boolean functions.

[BibT_eX]

[DOI]

Andrea Costamagna

Integr., March, 2023

AnySyn: A Cost-Generic Logic Synthesis Framework with Customizable Cost Functions.

[BibT_eX]

[DOI]

Hanyu Wang

CoRR, 2023

Synthesis of SFQ Circuits with Compound Gates.

[BibT_eX]

[DOI]

Proceedings of the 31st IFIP/IEEE International Conference on Very Large Scale Integration, 2023

Cyclical Progress in Design and Technology.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on Integrated Circuits, 2023

Striving for Both Quality and Speed: Logic Synthesis for Practical Garbled Circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Technology Mapping Using Multi-Output Library Cells.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer Aided Design, 2023

Generating Lower-Cost Garbled Circuits: Logic Synthesis Can Help.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2023

Compound Logic Gates for Pipeline Depth Minimization in Single Flux Quantum Integrated Systems.

[BibT_eX]

[DOI]

Proceedings of the Great Lakes Symposium on VLSI 2023, 2023

Fanout-Bounded Logic Synthesis for Emerging Technologies - A Top-Down Approach.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

Improving Standard-Cell Design Flow using Factored Form Optimization.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

Depth-Optimal Buffer and Splitter Insertion and Optimization in AQFP Circuits.

[BibT_eX]

[DOI]

Proceedings of the 28th Asia and South Pacific Design Automation Conference, 2023

Logic Synthesis for Emerging Technologies.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on ASIC, 2023

2022

A Simulation-Guided Paradigm for Logic Synthesis and Verification.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Advances in Quantum Computation and Quantum Technologies: A Design Automation Perspective.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Design and Automation for Quantum Computation and Quantum Technologies.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2022

Challenges and targets of MRAM-enabled scaled spintronic logic circuits.

[BibT_eX]

[DOI]

CoRR, 2022

An Automated Testing and Debugging Toolkit for Gate-Level Logic Synthesis Applications.

[BibT_eX]

[DOI]

CoRR, 2022

Efficient Deterministic Preparation of Quantum States Using Decision Diagrams.

[BibT_eX]

[DOI]

Fereshte Mozafari

Yuxiang Yang

CoRR, 2022

Logic Synthesis From Incomplete Specifications Using Disjoint Support Decomposition.

[BibT_eX]

[DOI]

Andrea Costamagna

Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

Design and Optimization of Quantum Electronic Circuits.

[BibT_eX]

[DOI]

Proceedings of the ISPD 2022: International Symposium on Physical Design, Virtual Event, Canada, March 27, 2022

tweedledum: A Compiler Companion for Quantum Computing.

[BibT_eX]

[DOI]

Bruno Schmitt

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Majority-based Design Flow for AQFP Superconducting Family.

[BibT_eX]

[DOI]

Proceedings of the 2022 Design, Automation & Test in Europe Conference & Exhibition, 2022

Beyond local optimality of buffer and splitter insertion for AQFP circuits.

[BibT_eX]

[DOI]

Proceedings of the DAC '22: 59th ACM/IEEE Design Automation Conference, San Francisco, California, USA, July 10, 2022

Boolean Rewriting Strikes Back: Reconvergence-Driven Windowing Meets Resynthesis.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

Efficient Preparation of Cyclic Quantum States.

[BibT_eX]

[DOI]

Fereshte Mozafari

Yuxiang Yang

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

A Versatile Mapping Approach for Technology Mapping and Graph Optimization.

[BibT_eX]

[DOI]

Proceedings of the 27th Asia and South Pacific Design Automation Conference, 2022

2021

Three-Input Gates for Logic Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2021

Real-Time Multi-Ion-Monitoring Front-End With Interference Compensation by Multi-Output Support Vector Regressor.

[BibT_eX]

[DOI]

Mandresy Ivan Ny Hanitra

Francesca Criscuolo

IEEE Trans. Biomed. Circuits Syst., 2021

The Emerging Majority: Technology and Design for Superconducting Electronics.

[BibT_eX]

[DOI]

IEEE Des. Test, 2021

Irredundant Buffer and Splitter Insertion and Scheduling-Based Optimization for AQFP Circuits.

[BibT_eX]

[DOI]

CoRR, 2021

Multi-Ion-Sensing Emulator and Multivariate Calibration Optimization by Machine Learning Models.

[BibT_eX]

[DOI]

IEEE Access, 2021

Optimizing Adiabatic Quantum-Flux-Parametron (AQFP) Circuits using an Exact Database.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2021

Logic Resynthesis of Majority-Based Circuits by Top-Down Decomposition.

[BibT_eX]

[DOI]

Proceedings of the 24th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2021

From Boolean functions to quantum circuits: A scalable quantum compilation flow in C++.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Compilation flow for classically defined quantum operations.

[BibT_eX]

[DOI]

Bruno Schmitt

Ali Javadi-Abhari

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Preserving Self-Duality During Logic Synthesis for Emerging Reconfigurable Nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

LUT-Based Optimization For ASIC Design Flow.

[BibT_eX]

[DOI]

Vinicius N. Possani

Eleonora Testa

Felipe S. Marranghello

Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

Algebraic and Boolean Optimization Methods for AQFP Superconducting Circuits.

[BibT_eX]

[DOI]

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

SAT-Based Exact Synthesis: Encodings, Topology Families, and Parallelism.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Advanced Functional Decomposition Using Majority and Its Applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Nonsilicon, Non-von Neumann Computing - Part II.

[BibT_eX]

[DOI]

Proc. IEEE, 2020

A Logic Synthesis Toolbox for Reducing the Multiplicative Complexity in Logic Networks.

[BibT_eX]

[DOI]

IACR Cryptol. ePrint Arch., 2020

2019 DAC Roundtable.

[BibT_eX]

[DOI]

Antun Domic

Massimiliano Di Ventra

Martin Roettler

Jason Cong

IEEE Des. Test, 2020

Simulation-Guided Boolean Resubstitution.

[BibT_eX]

[DOI]

CoRR, 2020

Extending Boolean Methods for Scalable Logic Synthesis.

[BibT_eX]

[DOI]

IEEE Access, 2020

Symbolic Algorithms for Token Swapping.

[BibT_eX]

[DOI]

Bruno Schmitt

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Automatic Uniform Quantum State Preparation Using Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the 50th IEEE International Symposium on Multiple-Valued Logic, 2020

Enumerating Optimal Quantum Circuits using Spectral Classification.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Emulator Design and Generation of Synthetic Dataset in Multi-Ion Sensing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2020

Multiplier Architectures: Challenges and Opportunities with Plasmonic-based Logic : (Special Session Paper).

[BibT_eX]

[DOI]

Proceedings of the 2020 Design, Automation & Test in Europe Conference & Exhibition, 2020

SAT-Sweeping Enhanced for Logic Synthesis.

[BibT_eX]

[DOI]

Luca G. Amarù

Felipe S. Marranghello

Proceedings of the 57th ACM/IEEE Design Automation Conference, 2020

2019

FPGA-SPICE: A Simulation-Based Architecture Evaluation Framework for FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2019

Devices and Circuits Using Novel 2-D Materials: A Perspective for Future VLSI Systems.

[BibT_eX]

[DOI]

Alexander Sanchez de la Cerda

IEEE Trans. Very Large Scale Integr. Syst., 2019

LUT-Based Hierarchical Reversible Logic Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Mapping Monotone Boolean Functions into Majority.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2019

Fast Procedures for the Electrodeposition of Platinum Nanostructures on Miniaturized Electrodes for Improved Ion Sensing.

[BibT_eX]

[DOI]

Sensors, 2019

Logic Synthesis for Established and Emerging Computing.

[BibT_eX]

[DOI]

Proc. IEEE, 2019

Nonsilicon, Non-von Neumann Computing - Part I [Scanning the Issue].

[BibT_eX]

[DOI]

Proc. IEEE, 2019

ROS: Resource-constrained Oracle Synthesis for Quantum Computers.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 16th International Conference on Quantum Physics and Logic, 2019

QubitHD: A Stochastic Acceleration Method for HD Computing-Based Machine Learning.

[BibT_eX]

[DOI]

Samuel Bosch

Mohsen Imani

CoRR, 2019

Evaluating ESOP Optimization Methods in Quantum Compilation Flows.

[BibT_eX]

[DOI]

Proceedings of the Reversible Computation - 11th International Conference, 2019

Multi-Target Electrolyte Sensing Front-End for Wearable Physical Monitoring.

[BibT_eX]

[DOI]

Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

Logic Optimization of Majority-Inverter Graphs.

[BibT_eX]

[DOI]

Proceedings of the 22nd Workshop Methods and Description Languages for Modelling and Verification of Circuits and Systems, 2019

All-solid-state Reference Electrodes for analytical applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE 8th International Workshop on Advances in Sensors and Interfaces, 2019

Scaling-up ESOP Synthesis for Quantum Compilation.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Reversible Pebble Games for Reducing Qubits in Hierarchical Quantum Circuit Synthesis.

[BibT_eX]

[DOI]

Debjyoti Bhattacharjee

Proceedings of the 2019 IEEE 49th International Symposium on Multiple-Valued Logic (ISMVL), 2019

Direct and Catalyst-Free Growth of Vertically-Stacked Graphene-Based Structures for Enhanced Drug Sensing.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Exact Synthesis of Boolean Functions in Majority-of-Five Forms.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

Flexible sweat sensors for non-invasive optimization of lithium dose in psychiatric disorders.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE SENSORS, Montreal, QC, Canada, October 27-30, 2019, 2019

The Role of Multiplicative Complexity in Compiling Low $T$-count Oracle Circuits.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2019

Scalable Boolean Methods in a Modern Synthesis Flow.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Compiling Permutations for Superconducting QPUs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

On-the-fly and DAG-aware: Rewriting Boolean Networks with Exact Synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Reversible Pebbling Game for Quantum Memory Management.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

Reducing the Multiplicative Complexity in Logic Networks for Cryptography and Security Applications.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Scalable Generic Logic Synthesis: One Approach to Rule Them All.

[BibT_eX]

[DOI]

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

AdaptHD: Adaptive Efficient Training for Brain-Inspired Hyperdimensional Computing.

[BibT_eX]

[DOI]

Proceedings of the 2019 IEEE Biomedical Circuits and Systems Conference, 2019

Structural rewriting in XOR-majority graphs.

[BibT_eX]

[DOI]

Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

Memory Effects in Multi-terminal Solid State Devices and Their Applications.

[BibT_eX]

[DOI]

Proceedings of the Handbook of Memristor Networks., 2019

2018

An IoT Solution for Online Monitoring of Anesthetics in Human Serum Based on an Integrated Fluidic Bioelectronic System.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2018

Towards Ultrasound Everywhere: A Portable 3D Digital Back-End Capable of Zone and Compound Imaging.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2018

Pairs of majority-decomposing functions.

[BibT_eX]

[DOI]

Inf. Process. Lett., 2018

Post-P&R Performance and Power Analysis for RRAM-Based FPGAs.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2018

Safe and Efficient Deployment of Data-Parallelizable Applications on Many-Core Platforms: Theory and Practice.

[BibT_eX]

[DOI]

IEEE Des. Test, 2018

Exact Synthesis of ESOP Forms.

[BibT_eX]

[DOI]

CoRR, 2018

The EPFL Logic Synthesis Libraries.

[BibT_eX]

[DOI]

CoRR, 2018

SAT-based {CNOT, T} Quantum Circuit Synthesis.

[BibT_eX]

[DOI]

Giulia Meuli

Proceedings of the Reversible Computation - 10th International Conference, 2018

Keynote Talk: NoCs: A Short History of Success and a Long Future.

[BibT_eX]

[DOI]

Proceedings of the Twelfth IEEE/ACM International Symposium on Networks-on-Chip, 2018

Size Optimization of MIGs with an Application to QCA and STMG Technologies.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE/ACM International Symposium on Nanoscale Architectures, 2018

A Flexible Front-End for Wearable Electrochemical Sensing.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE International Symposium on Medical Measurements and Applications, 2018

Generating Safety Guidance for Medical Injection with Three-Compartment Pharmacokinetics Model.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

End-to-End Industrial Study of Retiming.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE Computer Society Annual Symposium on VLSI, 2018

Portable Memristive Biosensing System as Effective Point-of-Care Device for Cancer Diagnostics.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Deep Learning for Logic Optimization Algorithms.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Mixed Gold and Platinum Nanostructured Layers for All-Solid-State Ion Sensors.

[BibT_eX]

[DOI]

Proceedings of the 2018 IEEE SENSORS, New Delhi, India, October 28-31, 2018, 2018

Integrated ESOP Refactoring for Industrial Designs.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

Majority logic synthesis.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Computer-Aided Design, 2018

A novel electrochemical sensor for non-invasive monitoring of lithium levels in mood disorders.

[BibT_eX]

[DOI]

Proceedings of the 40th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2018

Doping-free complementary inverter enabled by 2D WSe2 electrostatically-doped reconfigurable transistors.

[BibT_eX]

[DOI]

Proceedings of the 76th Device Research Conference, 2018

Practical exact synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Towards high-performance polarity-controllable FETs with 2D materials.

[BibT_eX]

[DOI]

Giovanni V. Resta

Jorge Romero Gonzalez

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Improvements to boolean resynthesis.

[BibT_eX]

[DOI]

Proceedings of the 2018 Design, Automation & Test in Europe Conference & Exhibition, 2018

Developing synthesis flows without human knowledge.

[BibT_eX]

[DOI]

Cunxi Yu

Houping Xiao

Proceedings of the 55th Annual Design Automation Conference, 2018

SAT based exact synthesis using DAG topology families.

[BibT_eX]

[DOI]

Proceedings of the 55th Annual Design Automation Conference, 2018

A best-fit mapping algorithm to facilitate ESOP-decomposition in Clifford+T quantum network synthesis.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

Functional decomposition using majority.

[BibT_eX]

[DOI]

Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017

A High-Performance FPGA Architecture Using One-Level RRAM-Based Multiplexers.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2017

Circuit Designs of High-Performance and Low-Power RRAM-Based Multiplexers Based on 4T(ransistor)1R(RAM) Programming Structure.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Cyber-Medical Systems: Requirements, Components and Design Examples.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2017

Exact Synthesis of Majority-Inverter Graphs and Its Applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

Efficient Sample Delay Calculation for 2-D and 3-D Ultrasound Imaging.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2017

A Differential Electrochemical Readout ASIC With Heterogeneous Integration of Bio-Nano Sensors for Amperometric Sensing.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2017

Nano-Tera.ch: Information Technology for Health, Environment, and Energy.

[BibT_eX]

[DOI]

Patrick Mayor

Martin Rajman

IEEE Des. Test, 2017

Logic Synthesis for Quantum Computing.

[BibT_eX]

[DOI]

CoRR, 2017

A PLiM Computer for the Internet of Things.

[BibT_eX]

[DOI]

Saeideh Shirinzadeh

Rolf Drechsler

Computer, 2017

Networks on Chips: 15 Years Later.

[BibT_eX]

[DOI]

Computer, 2017

Optimization opportunities in RRAM-based FPGA architectures.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Latin American Symposium on Circuits & Systems, 2017

An electrochemical sensor for quantitative analysis of Rhesus D antibodies in blood.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International Workshop on Advances in Sensors and Interfaces, 2017

Inverter Propagation and Fan-Out Constraints for Beyond-CMOS Majority-Based Technologies.

[BibT_eX]

[DOI]

Proceedings of the 2017 IEEE Computer Society Annual Symposium on VLSI, 2017

Physical Design Considerations of One-level RRAM-based Routing Multiplexers.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM on International Symposium on Physical Design, 2017

Classifying Functions with Exact Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 47th IEEE International Symposium on Multiple-Valued Logic, 2017

RM3 based logic synthesis (Special session paper).

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

An efficient electronic measurement interface for memristive biosensors.

[BibT_eX]

[DOI]

Sebastien Naus

Ioulia Tzouvadaki

Armando Biscontini

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

Enabling exact delay synthesis.

[BibT_eX]

[DOI]

Janet Olson

Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Improving Circuit Mapping Performance Through MIG-based Synthesis for Carry Chains.

[BibT_eX]

[DOI]

Proceedings of the on Great Lakes Symposium on VLSI 2017, 2017

Wave pipelining for majority-based beyond-CMOS technologies.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Design automation and design space exploration for quantum computers.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Busy man's synthesis: Combinational delay optimization with SAT.

[BibT_eX]

[DOI]

Alan Mishchenko

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Endurance management for resistive Logic-In-Memory computing architectures.

[BibT_eX]

[DOI]

Saeideh Shirinzadeh

Rolf Drechsler

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

1024-Channel 3D ultrasound digital beamformer in a single 5W FPGA.

[BibT_eX]

[DOI]

Federico Angiolini

Aya Ibrahim

William Andrew Simon

Marcel Arditi

Jean-Philippe Thiran

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Single-FPGA complete 3D and 2D medical ultrasound imager.

[BibT_eX]

[DOI]

Proceedings of the 2017 Conference on Design and Architectures for Signal and Image Processing, 2017

Hierarchical Reversible Logic Synthesis Using LUTs.

[BibT_eX]

[DOI]

Proceedings of the 54th Annual Design Automation Conference, 2017

Live demonstration: An IoT smartwatch-based system for intensive care monitoring.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Live demonstration: Inexpensive 1024-channel 3D telesonography system on FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Inexpensive 1024-channel 3D telesonography system on FPGA.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

Raspberry Pi driven flow-injection system for electrochemical continuous monitoring platforms.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2017

A novel basis for logic rewriting.

[BibT_eX]

[DOI]

Winston Haaswijk

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

Multi-level logic benchmarks: An exactness study.

[BibT_eX]

[DOI]

Proceedings of the 22nd Asia and South Pacific Design Automation Conference, 2017

2016

Memristive Biosensors Integration With Microfluidic Platform.

[BibT_eX]

[DOI]

Jean-François Delaloye

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

A Study on the Programming Structures for RRAM-Based FPGA Architectures.

[BibT_eX]

[DOI]

Gain Kim

IEEE Trans. Circuits Syst. I Regul. Pap., 2016

Efficient Statistical Parameter Selection for Nonlinear Modeling of Process/Performance Variation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

Majority-Inverter Graph: A New Paradigm for Logic Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2016

A Sound and Complete Axiomatization of Majority-n Logic.

[BibT_eX]

[DOI]

Anupam Chattopadhyay

IEEE Trans. Computers, 2016

A CMOS Amperometric System for Multi-Neurotransmitter Detection.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2016

In-Vivo Validation of Fully Implantable Multi-Panel Devices for Remote Monitoring of Metabolism.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2016

Design and analysis of jitter-aware low-power and high-speed TSV link for 3D ICs.

[BibT_eX]

[DOI]

Microelectron. J., 2016

Impact of data serialization over TSVs on routing congestion in 3D-stacked multi-core processors.

[BibT_eX]

[DOI]

Microelectron. J., 2016

A Fault-Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2016

Emerging Technology-Based Design of Primitives for Hardware Security.

[BibT_eX]

[DOI]

Yu Bi

Kaveh Shamsi

Jiann-Shiun Yuan

ACM J. Emerg. Technol. Comput. Syst., 2016

Co-Design of ReRAM Passive Crossbar Arrays Integrated in 180 nm CMOS Technology.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2016

Heuristic NPN Classification for Large Functions Using AIGs and LEXSAT.

[BibT_eX]

[DOI]

Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2016, 2016

Enumeration of Reversible Functions and Its Application to Circuit Complexity.

[BibT_eX]

[DOI]

Nabila Abdessaied

Proceedings of the Reversible Computation - 8th International Conference, 2016

Inversion optimization in Majority-Inverter Graphs.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2016

Paradigm-Shifting Players for IoT: Smart-Watches for Intensive Care Monitoring.

[BibT_eX]

[DOI]

Proceedings of the Wireless Mobile Communication and Healthcare, 2016

Notes on Majority Boolean Algebra.

[BibT_eX]

[DOI]

Anupam Chattopadhyay

Proceedings of the 46th IEEE International Symposium on Multiple-Valued Logic, 2016

Resistance impact by long connections on electrical behavior of integrated Memristive Biosensors.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

Simultaneous monitoring of anesthetics and therapeutic compounds with a portable multichannel potentiostat.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

An integrated platform for differential electrochemical and ISFET sensing.

[BibT_eX]

[DOI]

Pantelis Georgiou

Proceedings of the IEEE International Symposium on Circuits and Systems, 2016

One-step rapid synthesis of Au-Pt nanofems for electrochemical sensing and biosensing.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE SENSORS, Orlando, FL, USA, October 30 - November 3, 2016, 2016

Fast generation of lexicographic satisfiable assignments: enabling canonicity in SAT-based applications.

[BibT_eX]

[DOI]

Proceedings of the 35th International Conference on Computer-Aided Design, 2016

SAT-Based Combinational and Sequential Dependency Computation.

[BibT_eX]

[DOI]

Proceedings of the Hardware and Software: Verification and Testing, 2016

Single-FPGA 3D ultrasound beamformer.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Single-FPGA, scalable, low-power, and high-quality 3D ultrasound beamformer.

[BibT_eX]

[DOI]

William Andrew Simon

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

Fast hierarchical NPN classification.

[BibT_eX]

[DOI]

Proceedings of the 26th International Conference on Field Programmable Logic and Applications, 2016

A Full-Capacity Local RoutingArchitecture for FPGAs (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Nano-fabricated memristive biosensors for biomedical applications with liquid and dried samples.

[BibT_eX]

[DOI]

Proceedings of the 38th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2016

Optimizing Majority-Inverter Graphs with functional hashing.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

A power-efficient 3-D on-chip interconnect for multi-core accelerators with stacked L2 cache.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

The Programmable Logic-in-Memory (PLiM) computer.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Panel: Looking backwards and forwards.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Exploiting inherent characteristics of reversible circuits for faster combinational equivalence checking.

[BibT_eX]

[DOI]

Robert Wille

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

Demo: Efficient delay and apodization for on-FPGA 3D ultrasound.

[BibT_eX]

[DOI]

Proceedings of the 2016 Conference on Design and Architectures for Signal and Image Processing (DASIP), 2016

An MIG-based compiler for programmable logic-in-memory architectures.

[BibT_eX]

[DOI]

Saeideh Shirinzadeh

Rolf Drechsler

Proceedings of the 53rd Annual Design Automation Conference, 2016

Majority-based synthesis for nanotechnologies.

[BibT_eX]

[DOI]

Proceedings of the 21st Asia and South Pacific Design Automation Conference, 2016

2015

Cost-Effective Design of Mesh-of-Tree Interconnect for Multicore Clusters With 3-D Stacked L2 Scratchpad Memory.

[BibT_eX]

[DOI]

Kyungsu Kang

IEEE Trans. Very Large Scale Integr. Syst., 2015

A Novel FPGA Architecture Based on Ultrafine Grain Reconfigurable Logic Cells.

[BibT_eX]

[DOI]

Gain Kim

IEEE Trans. Very Large Scale Integr. Syst., 2015

Layout Technique for Double-Gate Silicon Nanowire FETs With an Efficient Sea-of-Tiles Architecture.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2015

New Logic Synthesis as Nanotechnology Enabler.

[BibT_eX]

[DOI]

Proc. IEEE, 2015

A Survey on Low-Power Techniques with Emerging Technologies: From Devices to Systems.

[BibT_eX]

[DOI]

Edith Beigné

Suzanne Lesecq

ACM J. Emerg. Technol. Comput. Syst., 2015

FRAME: Fast and Realistic Attacker Modeling and Evaluation for Temporal Logical Correlation in Static Noise.

[BibT_eX]

[DOI]

CoRR, 2015

NEM relay design with biconditional binary decision diagrams.

[BibT_eX]

[DOI]

Winston Haaswijk

Proceedings of the 2015 IEEE/ACM International Symposium on Nanoscale Architectures, 2015

A study on buffer distribution for RRAM-based FPGA routing structures.

[BibT_eX]

[DOI]

Somayyeh Rahimian Omam

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

A fast pruning technique for low-power inexact Circuit design.

[BibT_eX]

[DOI]

Johan Broc

Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015

Reliable redundancy with memristive-biosensors to achieve statistical significance in immunosensing.

[BibT_eX]

[DOI]

Proceedings of the 6th International Workshop on Advances in Sensors and Interfaces, 2015

On the Design of a Fault Tolerant Ripple-Carry Adder with Controllable-Polarity Transistors.

[BibT_eX]

[DOI]

Hassan Ghasemzadeh

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Exploiting Circuit Duality to Speed up SAT.

[BibT_eX]

[DOI]

Alan Mishchenko

Maciej J. Ciesielski

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Reversible Logic Synthesis via Biconditional Binary Decision Diagrams.

[BibT_eX]

[DOI]

Anupam Chattopadhyay

Alessandro Littarru

Proceedings of the 2015 IEEE International Symposium on Multiple-Valued Logic, 2015

Full system for translational studies of personalized medicine with free-moving mice.

[BibT_eX]

[DOI]

Sara Seyedeh Ghoreishizadeh

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

A neural approach to drugs monitoring for personalized medicine.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Joint Conference on Neural Networks, 2015

FPGA-SPICE: A simulation-based power estimation framework for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 33rd IEEE International Conference on Computer Design, 2015

Exploiting the Expressive Power of Graphene Reconfigurable Gates via Post-Synthesis Optimization.

[BibT_eX]

[DOI]

Proceedings of the 25th edition on Great Lakes Symposium on VLSI, GLVLSI 2015, Pittsburgh, PA, USA, May 20, 2015

Accurate power analysis for near-Vt RRAM-based FPGA.

[BibT_eX]

[DOI]

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

Towards More Efficient Logic Blocks By Exploiting Biconditional Expansion (Abstract Only).

[BibT_eX]

[DOI]

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

A surface potential and current model for polarity-controllable silicon nanowire FETs.

[BibT_eX]

[DOI]

Proceedings of the 45th European Solid State Device Research Conference, 2015

Fault modeling in controllable polarity silicon nanowire circuits.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Tackling the bottleneck of delay tables in 3D ultrasound imaging.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

A ultra-low-power FPGA based on monolithically integrated RRAMs.

[BibT_eX]

[DOI]

Jury Sandrini

Maxime Thammasack

Somayyeh Rahimian Omam

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

The future of electronics, semiconductors, and design in Europe: panel.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Wireless monitoring in intensive care units by a 3D-printed system with embedded electronic.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

Biocompatible packagings for fully implantable multi-panel devices for remote monitoring of metabolism.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2015

Multiple Independent Gate FETs: How many gates do we need?

[BibT_eX]

[DOI]

Gage Hills

Proceedings of the 20th Asia and South Pacific Design Automation Conference, 2015

2014

Configurable Circuits Featuring Dual-Threshold-Voltage Design With Three-Independent-Gate Silicon Nanowire FETs.

[BibT_eX]

[DOI]

Pascal Andreas Meinerzhagen

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

Energy/Reliability Trade-Offs in Low-Voltage ReRAM-Based Non-Volatile Flip-Flop Design.

[BibT_eX]

[DOI]

Ibrahim Kazi

IEEE Trans. Circuits Syst. I Regul. Pap., 2014

An Integrated Control and Readout Circuit for Implantable Multi-Target Electrochemical Biosensing.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2014

Full Fabrication and Packaging of an Implantable Multi-Panel Device for Monitoring of Metabolites in Small Animals.

[BibT_eX]

[DOI]

Enver G. Kilinc

IEEE Trans. Biomed. Circuits Syst., 2014

System Level Benchmarking with Yield-Enhanced Standard Cell Library for Carbon Nanotube VLSI Circuits.

[BibT_eX]

[DOI]

Jie Zhang

H.-S. Philip Wong

ACM J. Emerg. Technol. Comput. Syst., 2014

Representation of Medical Guidelines with a Computer Interpretable Model.

[BibT_eX]

[DOI]

Int. J. Artif. Intell. Tools, 2014

Biconditional Binary Decision Diagrams: A Novel Canonical Logic Representation Form.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2014

Novel configurable logic block architecture exploiting controllable-polarity transistors.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

Fast process variation analysis in nano-scaled technologies using column-wise sparse parameter selection.

[BibT_eX]

[DOI]

Majid Yazdani

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

Parallel vs. serial inter-plane communication using TSVs.

[BibT_eX]

[DOI]

Somayyeh Rahimian Omam

Proceedings of the IEEE 5th Latin American Symposium on Circuits and Systems, 2014

Unlocking Controllable-Polarity Transistors Opportunities by Exclusive-OR and Majority Logic Synthesis.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Temperature-aware runtime power management for chip-multiprocessors with 3-D stacked cache.

[BibT_eX]

[DOI]

Proceedings of the Fifteenth International Symposium on Quality Electronic Design, 2014

Novel grid-based power routing scheme for regular controllable-polarity FET arrangements.

[BibT_eX]

[DOI]

Odysseas Zografos

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

TSPC Flip-Flop circuit design with three-independent-gate silicon nanowire FETs.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Memristor-based devices for sensing.

[BibT_eX]

[DOI]

Francesca Puppo

Marie-Agnes Doucey

Massimiliano Di Ventra

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

Quantitative estimation of biological cell surface receptors by segmenting conventional fluorescence microscopy images.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

3D serial TSV link for low-power chip-to-chip communication.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on IC Design & Technology, 2014

A high-performance low-power near-Vt RRAM-based FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

Pattern-based FPGA logic block and clustering algorithm.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

A new basic logic structure for data-path computation (abstract only).

[BibT_eX]

[DOI]

Proceedings of the 2014 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2014

Electrochemical biochip for applications to wireless and batteryless monitoring of free-moving mice.

[BibT_eX]

[DOI]

Proceedings of the 36th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2014

Majority Logic Synthesis for Spin Wave Technology.

[BibT_eX]

[DOI]

Odysseas Zografos

Praveen Raghavan

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Advanced system on a chip design based on controllable-polarity FETs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Panel: Emerging vs. established technologies, a two sphinxes' riddle at the crossroads?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

An efficient manipulation package for Biconditional Binary Decision Diagrams.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Majority-Inverter Graph: A Novel Data-Structure and Algorithms for Efficient Logic Optimization.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

Novel readout circuit for memristive biosensors in cancer detection.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Glucose and lactate monitoring in cell cultures with a wireless android interface.

[BibT_eX]

[DOI]

Jacopo Olivo

Lorenzo Foglia

Maria Antonietta Casulli

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Programmable active pixel sensor for low-light biomedical applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

A lightweight cryptographic system for implantable biosensors.

[BibT_eX]

[DOI]

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Sub-mW reconfigurable interface IC for electrochemical sensing.

[BibT_eX]

[DOI]

Agnieszka Kinsner-Ovaskainen

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Live demonstration: A smart camera for real-time monitoring of fluorescent cell biomarkers.

[BibT_eX]

[DOI]

Julien Ghaye

Sinan K. Muldur

Patricia Urban

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Live demonstration: In-situ biosensors array for cell culture monitoring.

[BibT_eX]

[DOI]

Maria Antonietta Casulli

Proceedings of the IEEE Biomedical Circuits and Systems Conference, 2014

Safe Implementation of Embedded Software for a Portable Device Supporting Drug Administration.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE International Conference on Bioinformatics and Bioengineering, 2014

Data compression via logic synthesis.

[BibT_eX]

[DOI]

Andreas Burg

Proceedings of the 19th Asia and South Pacific Design Automation Conference, 2014

2013

Timing Uncertainty in 3-D Clock Trees Due to Process Variations and Power Supply Noise.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2013

QoS-Driven Reconfigurable Parallel Computing for NoC-Based Clustered MPSoCs.

[BibT_eX]

[DOI]

Eduard Fernandez-Alonso

Jordi Carrabina

IEEE Trans. Ind. Informatics, 2013

Designing best effort networks-on-chip to meet hard latency constraints.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., 2013

Power-Gated Differential Logic Style Based on Double-Gate Controllable-Polarity Transistors.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2013

Computing Accurate Performance Bounds for Best Effort Networks-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2013

A Study of Multi-Layer Spiral Inductors for Remote Powering of Implantable Sensors.

[BibT_eX]

[DOI]

Jacopo Olivo

IEEE Trans. Biomed. Circuits Syst., 2013

An integrated, programming model-driven framework for NoC-QoS support in cluster-based embedded many-cores.

[BibT_eX]

[DOI]

Parallel Comput., 2013

An Enhanced Design Methodology for Resonant Clock Trees.

[BibT_eX]

[DOI]

J. Low Power Electron., 2013

Cell transformations and physical design techniques for 3D monolithic integrated circuits.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2013

A combined sensor placement and convex optimization approach for thermal management in 3D-MPSoC with liquid cooling.

[BibT_eX]

[DOI]

Francesco Zanini

Integr., 2013

A ReRAM-based non-volatile flip-flop with sub-VT read and CMOS voltage-compatible write.

[BibT_eX]

[DOI]

Ibrahim Kazi

Pascal Meinerzhagen

Andreas Burg

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

Efficient arithmetic logic gates using double-gate silicon nanowire FETs.

[BibT_eX]

[DOI]

Luca Arnani

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

SATSoT: A methodology to map controllable-polarity devices on a regular fabric using SAT.

[BibT_eX]

[DOI]

Catherine Gasnier

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Vertically-stacked silicon nanowire transistors with controllable polarity: A robustness study.

[BibT_eX]

[DOI]

Hassan Ghasemzadeh

Proceedings of the 14th Latin American Test Workshop, 2013

Empirical study of noise dependence in electrochemical sensors.

[BibT_eX]

[DOI]

Gaurav Nanda

Proceedings of the 5th IEEE International Workshop on Advances in Sensors and Interfaces, 2013

Runtime 3-D stacked cache management for chip-multiprocessors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Quality Electronic Design, 2013

Dual-threshold-voltage configurable circuits with three-independent-gate silicon nanowire FETs.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Self-checking ripple-carry adder with Ambipolar Silicon NanoWire FET.

[BibT_eX]

[DOI]

Ogun Turkyilmaz

Fabien Clermidy

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Characterization of standard CMOS compatible photodiodes and pixels for Lab-on-Chip devices.

[BibT_eX]

[DOI]

Gozen Koklu

Ralph Etienne-Cummings

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

3.5-D integration: A case study.

[BibT_eX]

[DOI]

Ciprian Seiculescu

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

Parameterized SVM for personalized drug concentration prediction.

[BibT_eX]

[DOI]

Wenqi You

Alena Simalatsar

Proceedings of the 35th Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2013

A configurable IC to contol, readout, and calibrate an array of biosensors.

[BibT_eX]

[DOI]

Proceedings of the 21st European Conference on Circuit Theory and Design, 2013

A fast TCAD-based methodology for Variation analysis of emerging nano-devices.

[BibT_eX]

[DOI]

Majid Yazdani

Proceedings of the 2013 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2013

Electronic implants: power delivery and management.

[BibT_eX]

[DOI]

Jacopo Olivo

Proceedings of the Design, Automation and Test in Europe, 2013

Vertically-stacked double-gate nanowire FETs with controllable polarity: from devices to regular ASICs.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Panel: "will 3D-IC remain a technology of the future... even in the future?".

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Biconditional BDD: a novel canonical BDD for logic synthesis targeting XOR-rich circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2013

Towards structured ASICs using polarity-tunable Si nanowire transistors.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

BDS-MAJ: a BDD-based logic synthesis tool exploiting majority logic decomposition.

[BibT_eX]

[DOI]

Proceedings of the 50th Annual Design Automation Conference 2013, 2013

Nanogap-based enzymatic-free electrochemical detection of glucose.

[BibT_eX]

[DOI]

Ismael Rattalino

Paolo Motto Ros

Irene Taurino

Fernando Cortes-Salazar

Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

Multi-electrode amperometric biosensor for neurotransmitters detection.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

An implantable bio-micro-system for drug monitoring.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

Fabrication and packaging of a fully implantable biosensor array.

[BibT_eX]

[DOI]

Enver G. Kilinc

Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

MIXSyn: An efficient logic synthesis methodology for mixed XOR-AND/OR dominated circuits.

[BibT_eX]

[DOI]

Proceedings of the 18th Asia and South Pacific Design Automation Conference, 2013

2012

Online thermal control methods for multiprocessor systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2012

New Approaches for Carbon Nanotubes-Based Biosensors and Their Application to Cell Culture Monitoring.

[BibT_eX]

[DOI]

IEEE Trans. Biomed. Circuits Syst., 2012

Fully Integrated Biochip Platforms for Advanced Healthcare.

[BibT_eX]

[DOI]

Anthony Guiseppi-Elie

Sensors, 2012

Electrochemical Detection of Anti-Breast-Cancer Agents in Human Serum by Cytochrome P450-Coated Carbon Nanotubes.

[BibT_eX]

[DOI]

Sensors, 2012

Multiterminal Memristive Nanowire Devices for Logic and Memory Applications: A Review.

[BibT_eX]

[DOI]

Proc. IEEE, 2012

Inter-Plane Communication Methods for 3-D ICs.

[BibT_eX]

[DOI]

Somayyeh Rahimian

J. Low Power Electron., 2012

Effect of process variations in 3D global clock distribution networks.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2012

A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2012

Editorial.

[BibT_eX]

[DOI]

Maciej Ogorzalek

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A Self-Contained System With CNTs-Based Biosensors for Cell Culture Monitoring.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2012

A high-throughput and low-latency interconnection network for multi-core Clusters with 3-D stacked L2 tightly-coupled data memory.

[BibT_eX]

[DOI]

Kyungsu Kang

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

GMS: Generic memristive structure for non-volatile FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

Configurable Low-Latency Interconnect for Multi-core Clusters.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: From Algorithms to Circuits and System-on-Chip Design, 2012

3D-LIN: A configurable low-latency interconnect for multi-core clusters with 3D stacked L1 memory.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE/IFIP International Conference on VLSI and System-on-Chip, 2012

CCNoC: Specializing On-Chip Interconnects for Energy Efficiency in Cache-Coherent Servers.

[BibT_eX]

[DOI]

Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Process/design co-optimization of regular logic tiles for double-gate silicon nanowire transistors.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE/ACM International Symposium on Nanoscale Architectures, 2012

The combined effect of process variations and power supply noise on clock skew and jitter.

[BibT_eX]

[DOI]

Proceedings of the Thirteenth International Symposium on Quality Electronic Design, 2012

Quantitative comparison of commercial CCD and custom-designed CMOS camera for biological applications.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Enhanced wafer matching heuristics for 3-D ICs.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

TAT-based formal representation of medical guidelines: Imatinib case-study.

[BibT_eX]

[DOI]

Alena Simalatsar

Proceedings of the Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2012

Voltage propagation method for 3-D power grid analysis.

[BibT_eX]

[DOI]

Cheng Zhang

Proceedings of the 2012 Design, Automation & Test in Europe Conference & Exhibition, 2012

Integrated biosensors for personalized medicine.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors.

[BibT_eX]

[DOI]

Proceedings of the 49th Annual Design Automation Conference 2012, 2012

A distributed interleaving scheme for efficient access to WideIO DRAM memory.

[BibT_eX]

[DOI]

Ciprian Seiculescu

Proceedings of the 10th International Conference on Hardware/Software Codesign and System Synthesis, 2012

A current-mode potentiostat for multi-target detection tested with different lactate biosensors.

[BibT_eX]

[DOI]

Irene Taurino

Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012

Quantification of sub-resolution sized targets in cell fluorescent imaging.

[BibT_eX]

[DOI]

Julien Ghaye

Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012

Design, fabrication, and test of a sensor array for perspective biosensing in chronic pathologies.

[BibT_eX]

[DOI]

Andrea Cavallini

Proceedings of the 2012 IEEE Biomedical Circuits and Systems Conference, 2012

A Drug Administration Decision Support System.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Conference on Bioinformatics and Biomedicine Workshops, 2012

Medical guidelines reconciling medical software and electronic devices: Imatinib case-study.

[BibT_eX]

[DOI]

Alena Simalatsar

Proceedings of the 12th IEEE International Conference on Bioinformatics & Bioengineering, 2012

Engineering complex systems for health, security and the environment.

[BibT_eX]

[DOI]

Proceedings of the 17th Asia and South Pacific Design Automation Conference, 2012

2011

3D Network on Chip Topology Synthesis: Designing Custom Topologies for Chip Stacks.

[BibT_eX]

[DOI]

Proceedings of the 3D Integration for NoC-based SoC Architectures, 2011

An Efficient Gate Library for Ambipolar CNTFET Logic.

[BibT_eX]

[DOI]

Kartik Mohanram

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Hierarchical Thermal Management Policy for High-Performance 3D Systems With Liquid Cooling.

[BibT_eX]

[DOI]

IEEE J. Emerg. Sel. Topics Circuits Syst., 2011

HW-SW implementation of a decoupled FPU for ARM-based Cortex-M1 SoCs in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Industrial Embedded Systems (SIES), 2011

Convex-Based Thermal Management for 3D MPSoCs Using DVFS and Variable-Flow Liquid Cooling.

[BibT_eX]

[DOI]

Francesco Zanini

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

Design of Resonant Clock Distribution Networks for 3-D Integrated Circuits.

[BibT_eX]

[DOI]

Somayyeh Rahimian

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2011

A DRAM Centric NoC Architecture and Topology Design Approach.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

A Simulation Based Buffer Sizing Algorithm for Network on Chips.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2011

pH sensing with temperature compensation in a Molecular Biosensor for drugs detection.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on Quality Electronic Design, 2011

Thermal-aware system-level modeling and management for Multi-Processor Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Skew variability in 3-D ICs with multiple clock domains.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2011), 2011

Alternative design methodologies for the next generation logic switch.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE/ACM International Conference on Computer-Aided Design, 2011

PRO3D, Programming for Future 3D Manycore Architectures: Project's Interim Status.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods for Components and Objects, 10th International Symposium, 2011

Example-based support vector machine for drug concentration analysis.

[BibT_eX]

[DOI]

Wenqi You

Nicolas Widmer

Proceedings of the 33rd Annual International Conference of the IEEE Engineering in Medicine and Biology Society, 2011

Analytical heat transfer model for thermal through-silicon vias.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

An integrated platform for advanced diagnostics.

[BibT_eX]

[DOI]

Francesco Valgimigli

Proceedings of the Design, Automation and Test in Europe, 2011

Logic synthesis and physical design: Quo vadis?

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Personalized modeling for drug concentration prediction using Support Vector Machine.

[BibT_eX]

[DOI]

Wenqi You

Nicolas Widmer

Proceedings of the 4th International Conference on Biomedical Engineering and Informatics, 2011

CELONCEL: Effective design technique for 3-D monolithic integration targeting high performance integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 16th Asia South Pacific Design Automation Conference, 2011

Design and Analysis of NoCs for Low-Power 2D and 3D SoCs.

[BibT_eX]

[DOI]

Proceedings of the Low Power Networks-on-Chip., 2011

2010

Comparative Analysis of NoCs for Two-Dimensional Versus Three-Dimensional SoCs Supporting Multiple Voltage and Frequency Islands.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2010

SunFloor 3D: A Tool for Networks on Chip Topology Synthesis for 3-D Systems on Chips.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

Capacitance DNA bio-chips improved by new probe immobilization strategies.

[BibT_eX]

[DOI]

Microelectron. J., 2010

Process-induced skew variation for scaled 2-D and 3-D ICs.

[BibT_eX]

[DOI]

Proceedings of the International Workshop on System Level Interconnect Prediction Workshop, 2010

Regular fabric design with ambipolar CNTFETs for FPGA and structured ASIC applications.

[BibT_eX]

[DOI]

Michele De Marchi

Proceedings of the 2010 IEEE/ACM International Symposium on Nanoscale Architectures, 2010

Multicore thermal management using approximate explicit model predictive control.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Temperature sensor placement in thermal management systems for MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design aspects of carry lookahead adders with vertically-stacked nanowire transistors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Memristive devices fabricated with silicon nanowire schottky barrier transistors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Design of a CNFET array for sensing and control in P450 based biochips for multiple drug detection.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Characterization of memristive Poly-Si Nanowires via empirical physical modelling.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Physical design tradeoffs in power distribution networks for 3-D ICs.

[BibT_eX]

[DOI]

Ioannis Tsioutsios

Proceedings of the 17th IEEE International Conference on Electronics, 2010

Synthesis of regular computational fabrics with ambipolar CNTFET technology.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

Online convex optimization-based algorithm for thermal management of MPSoCs.

[BibT_eX]

[DOI]

Proceedings of the 20th ACM Great Lakes Symposium on VLSI 2009, 2010

A method to remove deadlocks in Networks-on-Chips with Wormhole flow control.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Power consumption of logic circuits in ambipolar carbon nanotube technology.

[BibT_eX]

[DOI]

Kartik Mohanram

Proceedings of the Design, Automation and Test in Europe, 2010

Panel: First commandment at least, do nothing well!

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2010

Carbon nanotube correlation: promising opportunity for CNFET circuit yield enhancement.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Networks on Chips: from research to products.

[BibT_eX]

[DOI]

Proceedings of the 47th Design Automation Conference, 2010

Exploring programming model-driven QoS support for NoC-based platforms.

[BibT_eX]

[DOI]

Proceedings of the 8th International Conference on Hardware/Software Codesign and System Synthesis, 2010

Methods for Designing Reliable Probe Arrays.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International Conference on Bioinformatics and Bioengineering, 2010

Design of networks on chips for 3D ICs.

[BibT_eX]

[DOI]

Proceedings of the 15th Asia South Pacific Design Automation Conference, 2010

Synchronization and power integrity issues in 3-D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE Asia Pacific Conference on Circuits and Systems, 2010

Performance analysis of 3-D monolithic integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Conference on 3D System Integration, 2010

2009

Processor Speed Control With Thermal Constraints.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Thermal Balancing Policy for Multiprocessor Stream Computing Platforms.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

An Outlook on Design Technologies for Future Integrated Systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Modeling stochasticity and robustness in gene regulatory networks.

[BibT_eX]

[DOI]

Bioinform., 2009

Repeater Insertion for Two-Terminal Nets in Three-Dimensional Integrated Circuits.

[BibT_eX]

[DOI]

Proceedings of the Nano-Net - 4th International ICST Conference, 2009

Quantum Dots and Wires to Improve Enzymes-Based Electrochemical Bio-sensing.

[BibT_eX]

[DOI]

Eugène David Ngangue Ndih

Proceedings of the Nano-Net - 4th International ICST Conference, 2009

A method for calculating hard QoS guarantees for Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 2009 International Conference on Computer-Aided Design, 2009

An Analytical Model for the Contention Access Period of the Slotted IEEE 802.15.4 with Service Differentiation.

[BibT_eX]

[DOI]

Nadia Khaled

Proceedings of IEEE International Conference on Communications, 2009

Power distribution paths in 3-D ICS.

[BibT_eX]

[DOI]

Ashoka Visweswara Sathanur

Proceedings of the 19th ACM Great Lakes Symposium on VLSI 2009, 2009

Multicore thermal management with model predictive control.

[BibT_eX]

[DOI]

Proceedings of the 19th European Conference on Circuit Theory and Design, 2009

SunFloor 3D: A tool for Networks On Chip topology synthesis for 3D systems on chips.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Physically clustered forward body biasing for variability compensation in nanometer CMOS design.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

Novel library of logic gates with ambipolar CNTFETs: Opportunities for multi-level logic synthesis.

[BibT_eX]

[DOI]

Kartik Mohanram

Proceedings of the Design, Automation and Test in Europe, 2009

Panel session - Consolidation, a modern "Moor of Venice" tale.

[BibT_eX]

[DOI]

Marco Casale-Rossi

Proceedings of the Design, Automation and Test in Europe, 2009

Design of compact imperfection-immune CNFET layouts for standard-cell-based logic synthesis.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2009

NoC topology synthesis for supporting shutdown of voltage islands in SoCs.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

Decoding nanowire arrays fabricated with the multi-spacer patterning technique.

[BibT_eX]

[DOI]

Proceedings of the 46th Design Automation Conference, 2009

Complete nanowire crossbar framework optimized for the multi-spacer patterning technique.

[BibT_eX]

[DOI]

Gianfranco Cerofolini

Proceedings of the 2009 International Conference on Compilers, 2009

Implementation of an Automated ECG-based Diagnosis Algorithm for a Wireless Body Sensor Plataform.

[BibT_eX]

Proceedings of the BIODEVICES 2009, 2009

A control theory approach for thermal balancing of MPSoC.

[BibT_eX]

[DOI]

Francesco Zanini

Francisco Gilabert Villamón

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Synthesis of networks on chips for 3D systems on chips.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

A stochastic perturbative approach to design a defect-aware thresholder in the sense amplifier of crossbar memories.

[BibT_eX]

[DOI]

Proceedings of the 14th Asia South Pacific Design Automation Conference, 2009

Networks-on-Chip: an Interconnect Fabric for Multiprocessor Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Embedded Systems Design and Verification, 2009

2008

Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

Joint hardware-software leakage minimization approach for the register file of VLIW embedded architectures.

[BibT_eX]

[DOI]

Integr., 2008

Network-on-Chip design and synthesis outlook.

[BibT_eX]

[DOI]

Integr., 2008

On-chip implementation of multiprocessor networks and switch fabrics.

[BibT_eX]

[DOI]

Int. J. Embed. Syst., 2008

Designing Micro- and Nanosystems for a Safer and Healthier Tomorrow.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2008

Joint co-clustering: Co-clustering of genomic and clinical bioimaging data.

[BibT_eX]

[DOI]

Comput. Math. Appl., 2008

Synchronous versus asynchronous modeling of gene regulatory networks.

[BibT_eX]

[DOI]

Bioinform., 2008

Stochastic modeling and analysis for environmentally powered wireless sensor nodes.

[BibT_eX]

[DOI]

Proceedings of the 6th International Symposium on Modeling and Optimization in Mobile, 2008

A Reconfigurable Network-on-Chip Architecture for Optimal Multi-Processor SoC Communication.

[BibT_eX]

[DOI]

Vincenzo Rana

Marco D. Santambrogio

Donatella Sciuto

Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

System-level design technologies for heterogeneous distributed systems.

[BibT_eX]

[DOI]

Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, 2008

OS-Based Sensor Node Platform and Energy Estimation Model for Health-Care Wireless Sensor Networks.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Temperature Control of High-Performance Multi-core Platforms Using Convex Optimization.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Thermal Balancing Policy for Streaming Computing on Multiprocessor Architectures.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Designing Micro/Nano Systems for a Safer and Healthier Tomorrow.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2008

Programmable logic circuits based on ambipolar CNFET.

[BibT_eX]

[DOI]

Proceedings of the 45th Design Automation Conference, 2008

Reliability-aware design for nanometer-scale devices.

[BibT_eX]

[DOI]

Michael DeBole

Vijaykrishnan Narayanan

Proceedings of the 13th Asia South Pacific Design Automation Conference, 2008

2007

A Method for Routing Packets Across Multiple Paths in NoCs with In-Order Delivery and Fault-Tolerance Gaurantees.

[BibT_eX]

[DOI]

VLSI Design, 2007

Power and Reliability Management of SoCs.

[BibT_eX]

[DOI]

Kresimir Mihic

IEEE Trans. Very Large Scale Integr. Syst., 2007

Synthesis of Predictable Networks-on-Chip-Based Interconnect Architectures for Chip Multiprocessors.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

HW-SW emulation framework for temperature-aware design in MPSoCs.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2007

Co-clustering: A Versatile Tool for Data Analysis in Biomedical Informatics.

[BibT_eX]

[DOI]

Sungroh Yoon

IEEE Trans. Inf. Technol. Biomed., 2007

Reconfiguration Strategies for Environmentally Powered Devices: Theoretical Analysis and Experimental Validation.

[BibT_eX]

[DOI]

Trans. High Perform. Embed. Archit. Compil., 2007

Timing-Error-Tolerant Network-on-Chip Design Methodology.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

An Application-Specific Design Methodology for On-Chip Crossbar Generation.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2007

Bringing NoCs to 65 nm.

[BibT_eX]

[DOI]

IEEE Micro, 2007

Clustering protein environments for function prediction: finding PROSITE motifs in 3D.

[BibT_eX]

[DOI]

BMC Bioinform., 2007

Dynamic simulation of regulatory networks using SQUAD.

[BibT_eX]

[DOI]

BMC Bioinform., 2007

Early wire characterization for predictable network-on-chip global interconnects.

[BibT_eX]

[DOI]

Proceedings of the Ninth International Workshop on System-Level Interconnect Prediction (SLIP 2007), 2007

An Efficient Method for Dynamic Analysis of Gene Regulatory Networks and <i>in silico</i> Gene Perturbation Experiments.

[BibT_eX]

[DOI]

Proceedings of the Research in Computational Molecular Biology, 2007

NoC Design and Implementation in 65nm Technology.

[BibT_eX]

[DOI]

Proceedings of the First International Symposium on Networks-on-Chips, 2007

Design Technologies for Networks on Chips.

[BibT_eX]

[DOI]

Proceedings of the First International Symposium on Networks-on-Chips, 2007

MiGra: A Task Migration Algorithm for Reducing Temperature Gradient in Multiprocessor Systems on Chip.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on System-on-Chip, 2007

Reduction of Register File Delay Due to Process Variability in VLIW Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

New Design Paradigms: New Architectures for New technologies.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

System-Level Design for Nano-Electronics.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Electronics, 2007

Fault-tolerant multi-level logic decoder for nanoscale crossbar memory arrays.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Computer-Aided Design, 2007

Multi-processor operating system emulation framework with thermal feedback for systems-on-chip.

[BibT_eX]

[DOI]

Salvatore Carta

Andrea Acquaviva

Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

Interactive presentation: Improving the fault tolerance of nanometric PLA designs.

[BibT_eX]

[DOI]

Proceedings of the 2007 Design, Automation and Test in Europe Conference and Exposition, 2007

Temperature-aware processor frequency assignment for MPSoCs using convex optimization.

[BibT_eX]

[DOI]

Proceedings of the 5th International Conference on Hardware/Software Codesign and System Synthesis, 2007

2006

A Pattern-Mining Method for High-Throughput Lab-on-a-Chip Data Analysis.

[BibT_eX]

[DOI]

Sungroh Yoon

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

Analysis and Optimization of MPSoC Reliability.

[BibT_eX]

[DOI]

J. Low Power Electron., 2006

A Complete Multi-Processor System-on-Chip FPGA-Based Emulation Framework.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2006, 2006

Designing Routing and Message-Dependent Deadlock Free Networks on Chips.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Research Trends in VLSI and Systems on Chip, 2006

Designing Message-Dependent Deadlock Free Networks on Chips for Application-Specific Systems on Chips.

[BibT_eX]

[DOI]

Proceedings of the IFIP VLSI-SoC 2006, 2006

Nanoelectronics: Challenges and Opportunities.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Compiler-Driven Leakage Energy Reduction in Banked Register Files.

[BibT_eX]

[DOI]

Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, 2006

Routing Aware Switch Hardware Customization for Networks on Chips.

[BibT_eX]

[DOI]

Proceedings of the 1st International ICST Conference on Nano-Networks, 2006

Comparison of a Timing-Error Tolerant Scheme with a Traditional Re-transmission Mechanism for Networks on Chips.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on System-on-Chip, 2006

Mining Gene Sets for Measuring Similarities.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Symposium on Computers and Communications (ISCC 2006), 2006

Reliability Support for On-Chip Memories Using Networks-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Computer Design (ICCD 2006), 2006

Designing application-specific networks on chips with floorplan information.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Computer-Aided Design, 2006

A simulation methodology for reliability analysis in multi-core SoCs.

[BibT_eX]

[DOI]

Ayse K. Coskun

Proceedings of the 16th ACM Great Lakes Symposium on VLSI 2006, Philadelphia, PA, USA, April 30, 2006

Exploiting Binary Abstractions in Deciphering Gene Interactions.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference of the IEEE Engineering in Medicine and Biology Society, 2006

A methodology for mapping multiple use-cases onto networks on chips.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

A multi-path routing strategy with guaranteed in-order packet delivery and fault-tolerance for networks on chip.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip.

[BibT_eX]

[DOI]

Proceedings of the 43rd Design Automation Conference, 2006

A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control.

[BibT_eX]

[DOI]

Proceedings of the 4th International Conference on Hardware/Software Codesign and System Synthesis, 2006

An opportunistic reconfiguration strategy for environmentally powered devices.

[BibT_eX]

[DOI]

Proceedings of the Third Conference on Computing Frontiers, 2006

Computer-Aided Evaluation of Protein Expression in Pathological Tissue Images.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Computer-Based Medical Systems (CBMS 2006), 2006

Mapping and configuration methods for multi-use-case networks on chips.

[BibT_eX]

[DOI]

Proceedings of the 2006 Conference on Asia South Pacific Design Automation: ASP-DAC 2006, 2006

Networks on chips - technology and tools.

[BibT_eX]

The Morgan Kaufmann series in systems on silicon, Elsevier Morgan Kaufmann, ISBN: 978-0-12-370521-1, 2006

2005

Network-on-Chip Design for Gigascale Systems-on-Chip.

[BibT_eX]

[DOI]

Proceedings of the Embedded Systems Handbook., 2005

A robust self-calibrating transmission scheme for on-chip networks.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

NoC Synthesis Flow for Customized Domain Specific Multiprocessor Systems-on-Chip.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2005

Discovering Coherent Biclusters from Gene Expression Data Using Zero-Suppressed Binary Decision Diagrams.

[BibT_eX]

[DOI]

IEEE ACM Trans. Comput. Biol. Bioinform., 2005

Error control schemes for on-chip communication links: the energy-reliability tradeoff.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2005

Design, Synthesis, and Test of Networks on Chips.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2005

Analysis of Error Recovery Schemes for Networks on Chips.

[BibT_eX]

[DOI]

Theo Theocharides

Narayanan Vijaykrishnan

Mary Jane Irwin

IEEE Des. Test Comput., 2005

IEEE Council for Electronic Design Automation: A new beginning.

[BibT_eX]

[DOI]

Al Dunlop

IEEE Des. Test Comput., 2005

Guest Editors' Introduction: The Network-on-Chip Paradigm in Practice and Research.

[BibT_eX]

[DOI]

André Ivanov

IEEE Des. Test Comput., 2005

Optimization of Reliability and Power Consumption in Systems on a Chip.

[BibT_eX]

[DOI]

Kresimir Mihic

Proceedings of the Integrated Circuit and System Design, 2005

Exploration and Tuning of Custom NoC Topologies Using an FPGA-Based Framework.

[BibT_eX]

Nicolas Genko

Proceedings of the Parallel Computing: Current & Future Issues of High-End Computing, 2005

Self-calibrating networks-on-chip.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A novel approach for network on chip emulation.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Plenary lecture [Second page is blank].

[BibT_eX]

[DOI]

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

Prediction of regulatory modules comprising microRNAs and target genes.

[BibT_eX]

[DOI]

Sungroh Yoon

Proceedings of the ECCB/JBI'05 Proceedings, Fourth European Conference on Computational Biology/Sixth Meeting of the Spanish Bioinformatics Network (Jornadas de BioInformática), Palacio de Congresos, Madrid, Spain, September 28, 2005

xpipes Lite: A Synthesis Oriented Design Library For Networks on Chips.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

An Application-Specific Design Methodology for STbus Crossbar Generation.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

A Complete Network-On-Chip Emulation Framework.

[BibT_eX]

[DOI]

Proceedings of the 2005 Design, 2005

Performance driven reliable link design for networks on chips.

[BibT_eX]

[DOI]

Rutuparna Tamhankar

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Mapping and physical planning of networks-on-chip architectures with quality-of-service guarantees.

[BibT_eX]

[DOI]

Proceedings of the 2005 Conference on Asia South Pacific Design Automation, 2005

Network On-Chip Design for Gigascale Systems-on-Chip.

[BibT_eX]

Proceedings of the Industrial Information Technology Handbook, 2005

2004

Specification and analysis of power-managed systems.

[BibT_eX]

[DOI]

Proc. IEEE, 2004

Packetization and routing analysis of on-chip multiprocessor networks.

[BibT_eX]

[DOI]

J. Syst. Archit., 2004

On-Chip Self-Calibrating Communication Techniques Robust to Electrical Parameter Variations.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2004

Reliability and Power Management of Integrated Systems.

[BibT_eX]

[DOI]

Kresimir Mihic

Proceedings of the 2004 Euromicro Symposium on Digital Systems Design (DSD 2004), Architectures, Methods and Tools, 31 August, 2004

Bandwidth-Constrained Mapping of Cores onto NoC Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

×pipesCompiler: A Tool for Instantiating Application Specific Networks on Chip.

[BibT_eX]

[DOI]

Proceedings of the 2004 Design, 2004

SUNMAP: a tool for automatic topology selection and generation for NoCs.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Reliable communication in systems on chips.

[BibT_eX]

[DOI]

Proceedings of the 41th Design Automation Conference, 2004

Enhanced pClustering and Its Applications to Gene Expression Data.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on BioInformatics and BioEngineering (BIBE 2004), 2004

Energy-Efficient Network-On-Chip Design.

[BibT_eX]

[DOI]

Proceedings of the Ultra Low-Power Electronics and Design, 2004

2003

Complex instruction and software library mapping for embedded software using symbolic algebra.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Application of symbolic computer algebra in high-level data-flow synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

CASS Brings Publishing to Its DAC Partnership.

[BibT_eX]

IEEE Des. Test Comput., 2003

Heterogeneous Wireless Network Management.

[BibT_eX]

[DOI]

Wajahat Qadeer

John Ankcorn

Venky Krishnan

Proceedings of the Power-Aware Computer Systems, Third International Workshop, 2003

Robust System Design with Uncertain Information.

[BibT_eX]

[DOI]

Proceedings of the 1st ACM & IEEE International Conference on Formal Methods and Models for Co-Design (MEMOCODE 2003), 2003

Packetized On-Chip Interconnect Communication Analysis for MPSoC.

[BibT_eX]

[DOI]

Proceedings of the 2003 Design, 2003

Physical Planning for On-Chip Multiprocessor Networks and Switch Fabrics.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

Automatic Instruction Set Extension and Utilization for Embedded Processors.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

Energy-Reliability trade-Off for NoCs.

[BibT_eX]

[DOI]

Proceedings of the Networks on Chip, 2003

2002

Power-aware operating systems for interactive systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2002

Dynamic frequency scaling with buffer insertion for mixed workloads.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Value-sensitive automatic code specialization for embedded software.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2002

Dynamic Power Management for Nonstationary Service Requests.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2002

Networks on Chips: A New SoC Paradigm.

[BibT_eX]

[DOI]

Computer, 2002

An Adaptive Low-Power Transmission Scheme for On-Chip Networks.

[BibT_eX]

[DOI]

Proceedings of the 15th International Symposium on System Synthesis (ISSS 2002), 2002

Contents provider-assisted dynamic voltage scaling for low energy multimedia applications.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Low Power Electronics and Design, 2002

Physical synthesis for ASIC datapath circuits.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Low Power Embedded Software Optimization Using Symbolic Algebra.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Networks on Chip: A New Paradigm for Systems on Chip Design.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Low Power Error Resilient Encoding for On-Chip Data Buses.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Analysis of power consumption on switch fabrics in network routers.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

Complex library mapping for embedded software using symbolic algebra.

[BibT_eX]

[DOI]

Proceedings of the 39th Design Automation Conference, 2002

Readings in hardware / software co-design.

[BibT_eX]

Rolf Ernst

Wayne H. Wolf

Morgan Kaufmann, ISBN: 978-1-55860-702-6, 2002

2001

Polynomial circuit models for component matching in high-level synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Energy-efficient design of battery-powered embedded systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2001

Synthesis of hardware models in C with pointers and complex data structures.

[BibT_eX]

[DOI]

Koichi Sato

IEEE Trans. Very Large Scale Integr. Syst., 2001

Event-driven power management.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Resolution, optimization, and encoding of pointer variables for thebehavioral synthesis from C.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Synthesis of power-managed sequential components based oncomputational kernel extraction.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2001

Comparing System-Level Power Management Policies.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2001

Cache-efficient memory layout of aggregate data structures.

[BibT_eX]

[DOI]

Preeti Ranjan Panda

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Source code transformation based on software cost analysis.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Powering Networks on Chips: Energy-Efficient and Reliable Interconnect Design for SoCs.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Systems Synthesis, 2001

Automatic source code specialization for energy reduction.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Symbolic Algebra and Timing Driven Data-flow Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 2001 IEEE/ACM International Conference on Computer-Aided Design, 2001

Component selection and matching for IP-based design.

[BibT_eX]

[DOI]

Ting Zhang

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Dynamic Voltage Scaling and Power Management for Portable Systems.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

Using Symbolic Algebra in Algorithmic Level DSP Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 38th Design Automation Conference, 2001

2000

Glitch power minimization by selective gate freezing.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

A survey of design techniques for system-level dynamic power management.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2000

Regression-based RTL power modeling.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2000

Synthesis of low-power selectively-clocked systems from high-level specification.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2000

System-level power optimization: techniques and tools.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2000

A multilevel engine for fast power simulation of realistic inputstreams.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2000

Hardware/Software Co-Design of Run-Time Schedulers for Real-Time Systems.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 2000

Dynamic power management for portable systems.

[BibT_eX]

[DOI]

Proceedings of the MOBICOM 2000, 2000

Source Code Optimization and Profiling of Energy Consumption in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 13th International Symposium on System Synthesis, 2000

Requester-Aware Power Reduction.

[BibT_eX]

[DOI]

Proceedings of the 13th International Symposium on System Synthesis, 2000

Energy efficient design of portable wireless systems.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Do our low-power tools have enough horse power? (panel session) (title only).

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Operating-system directed power reduction.

[BibT_eX]

[DOI]

Proceedings of the 2000 International Symposium on Low Power Electronics and Design, 2000

Data Path Placement with Regularity.

[BibT_eX]

[DOI]

Proceedings of the 2000 IEEE/ACM International Conference on Computer-Aided Design, 2000

Dynamic Power Management of Laptop Hard Disk.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C.

[BibT_eX]

[DOI]

Koichi Sato

Proceedings of the 2000 Design, 2000

Quantitative Comparison of Power Management Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 2000 Design, 2000

Low-power task scheduling for multiple devices.

[BibT_eX]

[DOI]

Proceedings of the Eighth International Workshop on Hardware/Software Codesign, 2000

1999

Symbolic synthesis of clock-gating logic for power optimization of synchronous controllers.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1999

Policy optimization for dynamic power management.

[BibT_eX]

[DOI]

Giuseppe A. Paleologo

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1999

Automatic Synthesis of Large Telescopic Units Based on Near-Minimum Timed Supersetting.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 1999

Reducing switching activity on datapath buses with control-signal gating.

[BibT_eX]

[DOI]

Hema Kapadia

IEEE J. Solid State Circuits, 1999

Event-Driven Power Management of Portable Systems.

[BibT_eX]

[DOI]

Proceedings of the 12th International Symposium on System Synthesis, 1999

Efficient switching activity computation during high-level synthesis of control-dominated designs.

[BibT_eX]

[DOI]

Proceedings of the 1999 International Symposium on Low Power Electronics and Design, 1999

Dynamic power management using adaptive learning tree.

[BibT_eX]

[DOI]

Proceedings of the 1999 IEEE/ACM International Conference on Computer-Aided Design, 1999

Adaptive Hard Disk Power Management on Personal Computers.

[BibT_eX]

[DOI]

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

Polynomial Methods for Allocating Complex Components.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Hardware Synthesis from C/C++ Models.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Dynamic Power Management for non-stationary service requests.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Glitch Power Minimization by Gate Freezing.

[BibT_eX]

[DOI]

Proceedings of the 1999 Design, 1999

Cycle-Accurate Simulation of Energy Consumption in Embedded Systems.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms.

[BibT_eX]

[DOI]

Proceedings of the 36th Conference on Design Automation, 1999

Software controlled power management.

[BibT_eX]

[DOI]

Proceedings of the Seventh International Workshop on Hardware/Software Codesign, 1999

1998

Power optimization of core-based systems by address bus encoding.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1998

Iterative remapping for logic circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Telescopic units: a new paradigm for performance optimization of VLSI designs.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1998

Regression Models for Behavioral Power Estimation.

[BibT_eX]

[DOI]

Integr. Comput. Aided Eng., 1998

Polynomial methods for component matching and verification.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

SpC: synthesis of pointers in C: application of pointer analysis to the behavioral synthesis from C.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Finding all simple disjunctive decompositions using irredundant sum-of-products forms.

[BibT_eX]

[DOI]

Shin-ichi Minato

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Dynamic power management of electronic systems.

[BibT_eX]

[DOI]

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

Reducing Power Consumption of Dedicated Processors Through Instruction Set Encoding.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Timed Supersetting and the Synthesis of Telescopic Units.

[BibT_eX]

[DOI]

Proceedings of the 8th Great Lakes Symposium on VLSI (GLS-VLSI '98), 1998

Acceleration of Satisfiability Algorithms by Reconfigurable Hardware.

[BibT_eX]

[DOI]

Marco Platzner

Proceedings of the Field-Programmable Logic and Applications, 1998

Hardware-Softw are Run-Time Systems and Robotics: A Case Study Vincent John Mooney III.

[BibT_eX]

[DOI]

Diego C. Ruspini

Oussama Khatib

Proceedings of the 24th EUROMICRO '98 Conference, 1998

Characterization-Free Behavioral Power Modeling.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

Address Bus Encoding Techniques for System-Level Power Optimization.

[BibT_eX]

[DOI]

Proceedings of the 1998 Design, 1998

Automated Composition of Hardware Components.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

Computational Kernels and their Application to Sequential Power Optimization.

[BibT_eX]

[DOI]

Proceedings of the 35th Conference on Design Automation, 1998

Dynamic power management - design techniques and CAD tools.

[BibT_eX]

Kluwer, ISBN: 978-0-7923-8086-3, 1998

1997

Clock Skew Optimization for Peak Current Reduction.

[BibT_eX]

[DOI]

J. VLSI Signal Process., 1997

Gate-level power and current simulation of CMOS integrated circuits.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 1997

A survey of Boolean matching techniques for library binding.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 1997

Specification and analysis of timing constraints for embedded systems.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1997

Constrained software synthesis for embedded applications.

[BibT_eX]

[DOI]

J. Syst. Archit., 1997

Re-mapping for low power under tight timing constraints.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

System-level power optimization of special purpose applications: the beach solution.

[BibT_eX]

[DOI]

Proceedings of the 1997 International Symposium on Low Power Electronics and Design, 1997

Generalized matching from theory to application.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Real time analysis and priority scheduler generation for hardware-software systems with a synthesized run-time system.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Fast power estimation for deterministic input streams.

[BibT_eX]

[DOI]

Proceedings of the 1997 IEEE/ACM International Conference on Computer-Aided Design, 1997

Asymptotic Zero-Transition Activity Encoding for Address Busses in Low-Power Microprocessor-Based Systems.

[BibT_eX]

[DOI]

Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997

Adaptive least mean square behavioral power modeling.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

Symbolic synthesis of clock-gating logic for power optimization of control-oriented synchronous networks.

[BibT_eX]

[DOI]

Proceedings of the European Design and Test Conference, 1997

1996

Scheduling and control generation with environmental constraints based on automata representations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Analysis and synthesis of concurrent digital circuits using control-flow expressions.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

Automatic synthesis of low-power gated-clock finite-state machines.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1996

A co-synthesis approach to embedded system design automation.

[BibT_eX]

[DOI]

Des. Autom. Embed. Syst., 1996

Synthesis of Low-Power Selectively-Clocked Systems from High-Level Specification.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on System Synthesis, 1996

Gate-level current waveform simulation of CMOS integrated circuits.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

Distributed EDA Tool Integration: The PPP Paradigm.

[BibT_eX]

[DOI]

Proceedings of the 1996 International Conference on Computer Design (ICCD '96), 1996

Synthesis from mixed specifications.

[BibT_eX]

[DOI]

Claudionor Nunes Coelho

Toshiyuki Sakamoto

Proceedings of the conference on European design automation, 1996

Design for Testability of Gated-Clock FSMs.

[BibT_eX]

[DOI]

Michele Favalli

Proceedings of the 1996 European Design and Test Conference, 1996

1995

State assignment for low power dissipation.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, March, 1995

Optimization of combinational logic circuits based on compatible gates.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1995

Transformation and synthesis of FSMs for low-power gated-clock implementation.

[BibT_eX]

[DOI]

Proceedings of the 1995 International Symposium on Low Power Design 1995, 1995

1994

Computer-aided hardware-software codesign.

[BibT_eX]

[DOI]

IEEE Micro, 1994

Saving Power by Synthesizing Gated Clocks for Sequential Circuits.

[BibT_eX]

[DOI]

Polly Siegel

IEEE Des. Test Comput., 1994

Program Implementation Schemes for Hardware-Software Systems.

[BibT_eX]

[DOI]

Computer, 1994

A Synthesis Framework Based on Trace and Automata Theory.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994

Decomposition methods for library binding of speed-independent asynchronous designs.

[BibT_eX]

[DOI]

Polly Siegel

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Dynamic scheduling and synchronization synthesis of concurrent digital systems under system-level constraints.

[BibT_eX]

[DOI]

Proceedings of the 1994 IEEE/ACM International Conference on Computer-Aided Design, 1994

Scheduling with Environmental Constraints based on Automata Representations.

[BibT_eX]

[DOI]

Proceedings of the EDAC - The European Conference on Design Automation, ETC - European Test Conference, EUROASIC - The European Event in ASIC Design, Proceedings, February 28, 1994

Constrained software generation for hardware-software systems.

[BibT_eX]

[DOI]

Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

Redesigning hardware-software systems.

[BibT_eX]

[DOI]

Proceedings of the Third International Workshop on Hardware/Software Codesign, 1994

1993

Interface optimization for concurrent systems under timing constraints.

[BibT_eX]

[DOI]

Dave Filo

IEEE Trans. Very Large Scale Integr. Syst., 1993

Designing high-performance digital circuits using wave pipelining: algorithms and practical experiences.

[BibT_eX]

[DOI]

Derek C. Wong

Michael J. Flynn

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Algorithms for technology mapping based on binary decision diagrams and on Boolean operations.

[BibT_eX]

[DOI]

Frédéric Mailhot

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Don't care set specifications in combinational and synchronous logic circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1993

Hardware-Software Cosynthesis for Digital Systems.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1993

High-Level Synthesis of Digital Circuits.

[BibT_eX]

[DOI]

Adv. Comput., 1993

Modeling hierarchical combinational circuits.

[BibT_eX]

[DOI]

Proceedings of the 1993 IEEE/ACM International Conference on Computer-Aided Design, 1993

Automatic Technology Mapping for Generalized Fundamental-Mode Asynchronous Designs.

[BibT_eX]

[DOI]

Polly Siegel

David L. Dill

Proceedings of the 30th Design Automation Conference. Dallas, 1993

1992

Relative scheduling under timing constraints: algorithms for high-level synthesis of digital circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1992

Optimizing the control-unit through the resynchronization of operations.

[BibT_eX]

[DOI]

David Filo

Integr., 1992

Synthesis and Simulation of Digital Systems Containing Interacting Hardware and Software Components.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

Recurrence Equations and the Optimization of Synchronous Logic Circuits.

[BibT_eX]

[DOI]

Proceedings of the 29th Design Automation Conference, 1992

1991

Synchronous logic synthesis: algorithms for cycle-time minimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1991

Optimal synthesis of control logic from behavioral specifications.

[BibT_eX]

[DOI]

Integr., 1991

Constrained resource sharing and conflict resolution in Hebe.

[BibT_eX]

[DOI]

Integr., 1991

Technology mapping for a two-output RAM-based field programmable gate array.

[BibT_eX]

[DOI]

Proceedings of the conference on European design automation, 1991

Control Optimization Based on Resynchronization of Operations.

[BibT_eX]

[DOI]

Dave Filo

Proceedings of the 28th Design Automation Conference, 1991

Technology Mapping for Electrically Programmable Gate Arrays.

[BibT_eX]

[DOI]

Silvia Ercolani

Proceedings of the 28th Design Automation Conference, 1991

1990

The Olympus Synthesis System.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 1990

Guest Editorial: High-Level Synthesis of Digital Circuits.

[BibT_eX]

IEEE Des. Test Comput., 1990

Partitioning of Functional Models of Synchronous Digital Systems.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Observability Don't Care Sets and Boolean Relations.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 1990

Technology mapping using boolean matching and don't care sets.

[BibT_eX]

[DOI]

Frédéric Mailhot

Proceedings of the European Design Automation Conference, 1990

Relative Scheduling Under Timing Constraints.

[BibT_eX]

[DOI]

Proceedings of the 27th ACM/IEEE Design Automation Conference. Orlando, 1990

1989

Inserting active delay elements to achieve wave pipelining.

[BibT_eX]

[DOI]

Derek C. Wong

Michael J. Flynn

Proceedings of the 1989 IEEE International Conference on Computer-Aided Design, 1989

1988

Automatic layout and optimization of static CMOS cells.

[BibT_eX]

[DOI]

Frédéric Mailhot

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

Approaching a nanosecond: a 32 bit adder.

[BibT_eX]

[DOI]

Proceedings of the Computer Design: VLSI in Computers and Processors, 1988

HERCULES - a System for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 25th ACM/IEEE Conference on Design Automation, 1988

1987

Performance-Oriented Synthesis of Large-Scale Domino CMOS Circuits.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1987

1986

Correction to "Optimal State Assignment for Finite State Machines".

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

Symbolic Design of Combinational and Sequential Logic Circuits Implemented by Two-Level Logic Macros.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1986

1985

Optimal State Assignment for Finite State Machines.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1985

1984

Correction to "Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications".

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1984

1983

Multiple Constrained Folding of Programmable Logic Arrays: Theory and Applications.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

Symmetric Displacement Algorithms for the Timing Analysis of Large Scale Circuits.

[BibT_eX]

[DOI]

A. Richard Newton

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 1983

PLEASURE: a computer program for simple/multiple constrained/unconstrained folding of Programmable Logic Arrays.

[BibT_eX]

[DOI]