Giovanni Brignone
Orcid: 0000-0002-1656-8376
According to our database1,
Giovanni Brignone
authored at least 5 papers
between 2022 and 2024.
Collaborative distances:
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Timeline
2022
2023
2024
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Bibliography
2024
SILVIA: Automated Superword-Level Parallelism Exploitation via HLS-Specific LLVM Passes for Compute-Intensive FPGA Accelerators.
CoRR, 2024
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024
2023
To Spike or Not to Spike: A Digital Hardware Perspective on Deep Learning Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., December, 2023
A DSP shared is a DSP earned: HLS Task-Level Multi-Pumping for High-Performance Low-Resource Designs.
Proceedings of the 41st IEEE International Conference on Computer Design, 2023
2022
Array-Specific Dataflow Caches for High-Level Synthesis of Memory-Intensive Algorithms on FPGAs.
IEEE Access, 2022