Giorgio Di Natale

IEEE Des. Test, December, 2024

Side Channel and Fault Analyses on Memristor-Based Logic In-Memory.

[BibT_eX]

[DOI]

Pietro Inglese

IEEE Des. Test, June, 2024

On Hardware Security and Trust for Chiplet-Based 2.5D and 3D ICs: Challenges and Innovations.

[BibT_eX]

[DOI]

IEEE Access, 2024

Internal State Monitoring in RISC-V Microarchitectures for Security Purpose.

[BibT_eX]

[DOI]

Roua Boulifa

Nasr-Eddine Ouldei Tebina

Paolo Maistri

Proceedings of the 25th IEEE Latin American Test Symposium, 2024

Non-Invasive Attack on Ring Oscillator-Based PUFs Through Localized X-Ray Irradiation.

[BibT_eX]

[DOI]

Aghiles Douadi

Luc Salvo

Vincent Beroulle

Nacer-Eddine Zergainoh

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2024

IEEE 1838 compliant scan encryption and integrity for 2.5/3D ICs.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2024

Modeling Thermal Effects For Biasing PUFs.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2024

Security Layers and Related Services within the Horizon Europe NEUROPULS Project.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

2023

Using Approximate Circuits Against Hardware Trojans.

[BibT_eX]

[DOI]

IEEE Des. Test, June, 2023

Introduction to the Special Issue on CAD for Security: Pre-silicon Security Sign-off Solutions Through Design Cycle.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., January, 2023

Python Framework for Modular and Parametric SPICE Netlists Generation.

[BibT_eX]

[DOI]

CoRR, 2023

NEUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.

[BibT_eX]

[DOI]

CoRR, 2023

On-Line Method to Limit Unreliability and Bit-Aliasing in RO-PUF.

[BibT_eX]

[DOI]

Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

Experimental Evaluation of Delayed-Based Detectors Against Power-off Attack.

[BibT_eX]

[DOI]

Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

A Study of High Temperature Effects on Ring Oscillator Based Physical Unclonable Functions.

[BibT_eX]

[DOI]

Proceedings of the 29th International Symposium on On-Line Testing and Robust System Design, 2023

EUROPULS: NEUROmorphic energy-efficient secure accelerators based on Phase change materials aUgmented siLicon photonicS.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2023

Open Automation Framework for Complex Parametric Electrical Simulations.

[BibT_eX]

[DOI]

Pietro Inglese

Haralampos-G. Stratigopoulos

Proceedings of the 26th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2023

2022

Digital-to-Analog Hardware Trojan Attacks.

[BibT_eX]

[DOI]

Marie-Minerve Louërat

Hassan Aboushady

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

Nonlinear Code-Based Low-Overhead Fine-Grained Control Flow Checking.

[BibT_eX]

[DOI]

Gilad Dar

Haralampos-G. Stratigopoulos

Osnat Keren

IEEE Trans. Computers, 2022

DETON: DEfeating hardware Trojan horses in microprocessors through software ObfuscatioN.

[BibT_eX]

[DOI]

J. Syst. Archit., 2022

Flexible and Portable Management of Secure Scan Implementations Exploiting P1687.1 Extensions.

[BibT_eX]

[DOI]

IEEE Des. Test, 2022

Helper Data Masking for Physically Unclonable Function-Based Key Generation Algorithms.

[BibT_eX]

[DOI]

Ashwija Reddy Korenda

Bertrand Cambou

IEEE Access, 2022

Circuit-to-Circuit Attacks in SoCs via Trojan-Infected IEEE 1687 Test Infrastructure.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2022

Secure PUF-based Authentication and Key Exchange Protocol using Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

An Efficient Approach to Model Strong PUF with Multi-Layer Perceptron using Transfer Learning.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Sub-Space Modeling: An Enrollment Solution for XOR Arbiter PUF using Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Symposium on Quality Electronic Design, 2022

Software Product Reliability Based on Basic Block Metrics Recomposition.

[BibT_eX]

[DOI]

Proceedings of the 28th IEEE International Symposium on On-Line Testing and Robust System Design, 2022

On-Line Reliability Estimation of Ring Oscillator PUF.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2022

On the optimization of Software Obfuscation against Hardware Trojans in Microprocessors.

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

Dependability of Alternative Computing Paradigms for Machine Learning: hype or hope?

[BibT_eX]

[DOI]

Proceedings of the 25th International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2022

Elaborating on Sub-Space Modeling as an Enrollment Solution for Strong PUF.

[BibT_eX]

[DOI]

Proceedings of the 18th International Conference on Distributed Computing in Sensor Systems, 2022

2021

Security EDA Extension through P1687.1 and 1687 Callbacks.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Test Conference, 2021

Automated Dysfunctional Model Extraction for Model Based Safety Assessment of Digital Systems.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE International Symposium on On-Line Testing and Robust System Design, 2021

Design Space Exploration Applied to Security.

[BibT_eX]

[DOI]

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

On the Limitations of Concatenating Boolean Operations in Memristive-Based Logic-In-Memory Solutions.

[BibT_eX]

[DOI]

Pietro Inglese

Proceedings of the 16th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2021

Identification of Hardware Devices based on Sensors and Switching Activity: a Preliminary Study.

[BibT_eX]

[DOI]

Honorio Martín

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

Scramble Cache: An Efficient Cache Architecture for Randomized Set Permutation.

[BibT_eX]

[DOI]

Amine Jaamoum

Thomas Hiscock

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2021

2020

Holding Conferences Online due to COVID-19: The DATE Experience.

[BibT_eX]

[DOI]

Cristiana Bolchini

IEEE Des. Test, 2020

Machine Learning and Hardware security: Challenges and Opportunities -Invited Talk-.

[BibT_eX]

[DOI]

Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2020

Nonlinear Codes for Control Flow Checking.

[BibT_eX]

[DOI]

Osnat Keren

Proceedings of the IEEE European Test Symposium, 2020

Hardware Trojan Attacks in Analog/Mixed-Signal ICs via the Test Access Mechanism.

[BibT_eX]

[DOI]

Mohamed Elshamy

Haralampos-G. D. Stratigopoulos

Antonios Pavlidis

Marie-Minerve Louërat

Proceedings of the IEEE European Test Symposium, 2020

PUF Enrollment and Life Cycle Management: Solutions and Perspectives for the Test Community.

[BibT_eX]

[DOI]

Proceedings of the IEEE European Test Symposium, 2020

Latest Trends in Hardware Security and Privacy.

[BibT_eX]

[DOI]

Abderrahmane Sensaoui

Samuel Pagliarini

Proceedings of the IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2020

2019

High-Entropy STT-MTJ-Based TRNG.

[BibT_eX]

[DOI]

Athanasios Chatzidimitriou

IEEE Trans. Very Large Scale Integr. Syst., 2019

Preventing Scan Attacks on Secure Circuits Through Scan Chain Encryption.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

SyRA: Early System Reliability Analysis for Cross-Layer Soft Errors Resilience in Memory Arrays of Microprocessor Systems.

[BibT_eX]

[DOI]

Alessandro Vallero

Alessandro Savino

IEEE Trans. Computers, 2019

Stream vs block ciphers for scan encryption.

[BibT_eX]

[DOI]

Microelectron. J., 2019

Memory-Aware Design Space Exploration for Reliability Evaluation in Computing Systems.

[BibT_eX]

[DOI]

Maha Kooli

J. Electron. Test., 2019

A Survey on Security Threats and Countermeasures in IEEE Test Standards.

[BibT_eX]

[DOI]

IEEE Des. Test, 2019

SECCS: SECure Context Saving for IoT Devices.

[BibT_eX]

[DOI]

CoRR, 2019

Special Session: Reliability of Hardware-Implemented Spiking Neural Networks (SNN).

[BibT_eX]

[DOI]

Lorena Anghel

Proceedings of the 37th IEEE VLSI Test Symposium, 2019

A Comprehensive Approach to a Trusted Test Infrastructure.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

On the Reliability of the Ring Oscillator Physically Unclonable Functions.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Verification and Security Workshop, 2019

On the Encryption of the Challenge in Physically Unclonable Functions.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

HATE: a HArdware Trojan Emulation Environment for Microprocessor-based Systems.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE International Symposium on On-Line Testing and Robust System Design, 2019

Alternatives to Fault Injections for Early Safety/Security Evaluations.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE European Test Symposium, 2019

Providing Confidentiality and Integrity in Ultra Low Power IoT Devices.

[BibT_eX]

[DOI]

Proceedings of the 14th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2019

Rebooting Computing: The Challenges for Test and Reliability.

[BibT_eX]

[DOI]

Gennaro Severino Rodrigues

Ian O'Connor

Fernanda Lima Kastensmidt

Proceedings of the 2019 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2019

Encryption-Based Secure JTAG.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2019

Hidden-Delay-Fault Sensor for Test, Reliability and Security.

[BibT_eX]

[DOI]

Kalpana Senthamarai Kannan

Lorena Anghel

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

2018

Guest Editorial: IEEE Transactions on Emerging Topics in Computing Special Issue on Design & Technology of Integrated Systems in Deep Submicron Era.

[BibT_eX]

[DOI]

Marco Ottavi

IEEE Trans. Emerg. Top. Comput., 2018

Towards a Dependable True Random Number Generator With Self-Repair Capabilities.

[BibT_eX]

[DOI]

Honorio Martín

Raphael Andreoni Camponogara Viera

Luis Entrena

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

A Ring Oscillator-Based Identification Mechanism Immune to Aging and External Working Conditions.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. I Regul. Pap., 2018

Assessing body built-in current sensors for detection of multiple transient faults.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2018

Protection Against Hardware Trojans With Logic Testing: Proposed Solutions and Challenges Ahead.

[BibT_eX]

[DOI]

IEEE Des. Test, 2018

Neuromorphic Computing - From Robust Hardware Architectures to Testing Strategies.

[BibT_eX]

[DOI]

Proceedings of the IFIP/IEEE International Conference on Very Large Scale Integration, 2018

Encryption of test data: which cipher is better?

[BibT_eX]

[DOI]

Proceedings of the 14th Conference on Ph.D. Research in Microelectronics and Electronics, 2018

A New Secure Stream Cipher for Scan Chain Encryption.

[BibT_eX]

[DOI]

Proceedings of the 3rd IEEE International Verification and Security Workshop, 2018

A Novel Use of Approximate Circuits to Thwart Hardware Trojan Insertion and Provide Obfuscation.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

The case of using CMOS FD-SOI rather than CMOS bulk to harden ICs against laser attacks.

[BibT_eX]

[DOI]

Jean-Max Dutertre

Vincent Beroulle

Philippe Candelier

Louis-Barthelemy Faber

Proceedings of the 24th IEEE International Symposium on On-Line Testing And Robust System Design, 2018

Laser Fault Injection at the CMOS 28 nm Technology Node: an Analysis of the Fault Model.

[BibT_eX]

[DOI]

Louis-Barthelemy Faber

Proceedings of the 2018 Workshop on Fault Diagnosis and Tolerance in Cryptography, 2018

SI ECCS: SECure context saving for IoT devices.

[BibT_eX]

[DOI]

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

2017

Computing reliability: On the differences between software testing and software fault injection techniques.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2017

Report on DATE 2017 in Lausanne.

[BibT_eX]

[DOI]

David Atienza

IEEE Des. Test, 2017

Zero bit-error-rate weak PUF based on Spin-Transfer-Torque MRAM memories.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Experimentations on scan chain encryption with PRESENT.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Hacking the Control Flow error detection mechanism.

[BibT_eX]

[DOI]

Proceedings of the IEEE 2nd International Verification and Security Workshop, 2017

Reliability of computing systems: From flip flops to variables.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on On-Line Testing and Robust System Design, 2017

Scan chain encryption for the test, diagnosis and debug of secure circuits.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE European Test Symposium, 2017

Do we need a holistic approach for the design of secure IoT systems?

[BibT_eX]

[DOI]

Proceedings of the Computing Frontiers Conference, 2017

2016

Editorial.

[BibT_eX]

[DOI]

Stefano Zanero

IEEE Trans. Emerg. Top. Comput., 2016

Introduction to Special Issue on Trustworthy Manufacturing and Utilization of Secure Devices (TRUDEVICE).

[BibT_eX]

[DOI]

Lilian Bossuet

Paris Kitsos

Microprocess. Microsystems, 2016

Ring oscillators analysis for security purposes in Spartan-6 FPGAs.

[BibT_eX]

[DOI]

Mario Barbareschi

Lionel Torres

Microprocess. Microsystems, 2016

STT-MRAM-Based PUF Architecture Exploiting Magnetic Tunnel Junction Fabrication-Induced Variability.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2016

Frontside Versus Backside Laser Injection: A Comparative Study.

[BibT_eX]

[DOI]

ACM J. Emerg. Technol. Comput. Syst., 2016

Security primitives (PUF and TRNG) with STT-MRAM.

[BibT_eX]

[DOI]

Athanasios Chatzidimitriou

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Cache- and register-aware system reliability evaluation based on data lifetime analysis.

[BibT_eX]

[DOI]

Proceedings of the 34th IEEE VLSI Test Symposium, 2016

Faster-than-at-speed execution of functional programs: An experimental analysis.

[BibT_eX]

[DOI]

Proceedings of the 2016 IFIP/IEEE International Conference on Very Large Scale Integration, 2016

Improving Stress Quality for SoC Using Faster-than-At-Speed Execution of Functional Programs.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: System-on-Chip in the Nanoscale Era - Design, Verification and Reliability, 2016

Using outliers to detect stealthy hardware trojan triggering?

[BibT_eX]

[DOI]

Proceedings of the 1st IEEE International Verification and Security Workshop, 2016

Cross-layer system reliability assessment framework for hardware faults.

[BibT_eX]

[DOI]

Proceedings of the 2016 IEEE International Test Conference, 2016

Hardware Trust through Layout Filling: A Hardware Trojan Prevention Technique.

[BibT_eX]

[DOI]

Papa-Sidi Ba

Sophie Dupuis

Palanichamy Manikandan

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2016

STT-MTJ-based TRNG with on-the-fly temperature/current variation compensation.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Cache-aware reliability evaluation through LLVM-based analysis and fault injection.

[BibT_eX]

[DOI]

Maha Kooli

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

Revisiting software-based soft error mitigation techniques via accurate error generation and propagation models.

[BibT_eX]

[DOI]

Mojtaba Ebrahimi

Maryam Rashvand

Firas Kaddachi

Mehdi Baradaran Tahoori

Haralampos-G. D. Stratigopoulos

Proceedings of the 22nd IEEE International Symposium on On-Line Testing and Robust System Design, 2016

ETS 2016 foreword.

[BibT_eX]

[DOI]

Proceedings of the 21th IEEE European Test Symposium, 2016

SEcube™: An open-source security platform in a single SoC.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Design and Technology of Integrated Systems in Nanoscale Era, 2016

System-level reliability evaluation through cache-aware software-based fault injection.

[BibT_eX]

[DOI]

Mehdi Baradaran Tahoori

Proceedings of the 2016 IEEE 19th International Symposium on Design and Diagnostics of Electronic Circuits & Systems (DDECS), 2016

Towards a highly reliable SRAM-based PUFs.

[BibT_eX]

[DOI]

Proceedings of the 2016 Design, Automation & Test in Europe Conference & Exhibition, 2016

2015

Cross-layer reliability evaluation, moving from the hardware architecture to the system level: A CLERECO EU project overview.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2015

STT-MRAM-Based Strong PUF Architecture.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Digital Right Management for IP Protection.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

3D DFT Challenges and Solutions.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Figure of Merits of 28nm Si Technologies for Implementing Laser Attack Resistant Security Dedicated Circuits.

[BibT_eX]

[DOI]

Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015

Challenges in designing trustworthy cryptographic co-processors.

[BibT_eX]

[DOI]

Apostolos P. Fournaris

Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

Session-less based thermal-aware 3D-SIC test scheduling.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE European Test Symposium, 2015

Hardware Trojan prevention using layout-level design approach.

[BibT_eX]

[DOI]

Papa-Sidi Ba

Palanichamy Manikandan

Proceedings of the European Conference on Circuit Theory and Design, 2015

DTIS 2015 foreword.

[BibT_eX]

[DOI]

Proceedings of the 10th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2015

STT MRAM-Based PUFs.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

New testing procedure for finding insertion sites of stealthy hardware trojans.

[BibT_eX]

[DOI]

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

2014

Thwarting Scan-Based Attacks on Secure-ICs With On-Chip Comparison.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2014

Test Versus Security: Past and Present.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2014

Improving the ability of Bulk Built-In Current Sensors to detect Single Event Effects by using triple-well CMOS.

[BibT_eX]

[DOI]

Jean-Max Dutertre

Microelectron. Reliab., 2014

Testing Methods for PUF-Based Secure Key Storage Circuits.

[BibT_eX]

[DOI]

J. Electron. Test., 2014

Built-in self-test for manufacturing TSV defects before bonding.

[BibT_eX]

[DOI]

Proceedings of the 32nd IEEE VLSI Test Symposium, 2014

Laser-induced fault effects in security-dedicated circuits.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014

Laser-Induced Fault Effects in Security-Dedicated Circuits.

[BibT_eX]

[DOI]

Clément Tavernier

Pierre Vanhauwaert

Proceedings of the VLSI-SoC: Internet of Things Foundations, 2014

Fault injection tools based on Virtual Machines.

[BibT_eX]

[DOI]

Proceedings of the 9th International Symposium on Reconfigurable and Communication-Centric Systems-on-Chip, 2014

2D to 3D Test Pattern Retargeting Using IEEE P1687 Based 3D DFT Architectures.

[BibT_eX]

[DOI]

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2014

Customized cell detector for laser-induced-fault detection.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A novel hardware logic encryption technique for thwarting illegal overproduction and Hardware Trojans.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

Cross-layer early reliability evaluation: Challenges and promises.

[BibT_eX]

[DOI]

Proceedings of the 2014 IEEE 20th International On-Line Testing Symposium, 2014

A novel adaptive fault tolerant flip-flop architecture based on TMR.

[BibT_eX]

[DOI]

Luca Cassano

Proceedings of the 19th IEEE European Test Symposium, 2014

DTIS 2014 foreword.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Layout-aware laser fault injection simulation and modeling: From physical level to gate level.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

A survey on simulation-based fault injection tools for complex systems.

[BibT_eX]

[DOI]

Maha Kooli

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Laser attacks on integrated circuits: From CMOS to FD-SOI.

[BibT_eX]

[DOI]

Proceedings of the 9th International Conference on Design & Technology of Integrated Systems in Nanoscale Era, 2014

Cross-Layer Early Reliability Evaluation for the Computing cOntinuum.

[BibT_eX]

[DOI]

Proceedings of the 17th Euromicro Conference on Digital System Design, 2014

Hacking and protecting IC hardware.

[BibT_eX]

[DOI]

Said Hamdioui

Jean-Luc Danger

Fethulah Smailbegovic

Gerard van Battum

Mark M. Tehranipoor

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

Testing PUF-based secure key storage circuits.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2014

2013

A novel differential scan attack on advanced DFT structures.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2013

Sensitivity tuning of a bulk built-in current sensor for optimal transient-fault detection.

[BibT_eX]

[DOI]

Jean-Max Dutertre

Microelectron. Reliab., 2013

TRUDEVICE: A COST Action on Trustworthy Manufacturing and Utilization of Secure Devices.

[BibT_eX]

[DOI]

Inf. Secur. J. A Glob. Perspect., 2013

Multilevel Ionizing-Induced Transient Fault Simulator.

[BibT_eX]

[DOI]

Inf. Secur. J. A Glob. Perspect., 2013

On the Effectiveness of Hardware Trojan Horse Detection via Side-Channel Analysis.

[BibT_eX]

[DOI]

Inf. Secur. J. A Glob. Perspect., 2013

Secure JTAG Implementation Using Schnorr Protocol.

[BibT_eX]

[DOI]

J. Electron. Test., 2013

A New Recovery Scheme Against Short-to-Long Duration Transient Faults in Combinational Logic.

[BibT_eX]

[DOI]

J. Electron. Test., 2013

A single built-in sensor to check pull-up and pull-down CMOS networks against transient faults.

[BibT_eX]

[DOI]

Proceedings of the 2013 23rd International Workshop on Power and Timing Modeling, 2013

A 3D IC BIST for pre-bond test of TSVs using ring oscillators.

[BibT_eX]

[DOI]

Proceedings of the IEEE 11th International New Circuits and Systems Conference, 2013

A smart test controller for scan chains in secure circuits.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE 19th International On-Line Testing Symposium (IOLTS), 2013

A BIST method for TSVs pre-bond test.

[BibT_eX]

[DOI]

Proceedings of the 8th International Design and Test Symposium, 2013

A bulk built-in sensor for detection of fault attacks.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Hardware-Oriented Security and Trust, 2013

Laser-Induced Fault Simulation.

[BibT_eX]

[DOI]

Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

2012

On Countermeasures Against Fault Attacks on the Advanced Encryption Standard.

[BibT_eX]

[DOI]

Proceedings of the Fault Analysis in Cryptography, 2012

Statistical Reliability Estimation of Microprocessor-Based Systems.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2012

Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode.

[BibT_eX]

[DOI]

Microelectron. Reliab., 2012

Scan attacks on side-channel and fault attack resistant public-key implementations.

[BibT_eX]

[DOI]

J. Cryptogr. Eng., 2012

Are advanced DfT structures sufficient for preventing scan-attacks?

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE VLSI Test Symposium, 2012

On-chip test comparison for protecting confidential data in secure ICs.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE European Test Symposium, 2012

A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2012

A New Scan Attack on RSA in Presence of Industrial Countermeasures.

[BibT_eX]

[DOI]

Proceedings of the Constructive Side-Channel Analysis and Secure Design, 2012

2011

Timing issues for an efficient use of concurrent error detection codes.

[BibT_eX]

[DOI]

Proceedings of the 12th Latin American Test Workshop, 2011

New security threats against chips containing scan chain structures.

[BibT_eX]

[DOI]

Proceedings of the HOST 2011, 2011

Scan Attacks and Countermeasures in Presence of Scan Response Compactors.

[BibT_eX]

[DOI]

Proceedings of the 16th European Test Symposium, 2011

A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies.

[BibT_eX]

[DOI]

Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

Power consumption traces realignment to improve differential power analysis.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011

2010

Self-Test Techniques for Crypto-Devices.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2010

Evaluation of concurrent error detection techniques on the Advanced Encryption Standard.

[BibT_eX]

[DOI]

Proceedings of the 15th European Test Symposium, 2010

Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers.

[BibT_eX]

[DOI]

Proceedings of the Fifth IEEE International Symposium on Electronic Design, 2010

Ensuring high testability without degrading security: Embedded tutorial on "test and security".

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE International Symposium on Design and Diagnostics of Electronic Circuits and Systems, 2010

2009

A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard.

[BibT_eX]

[DOI]

J. Electron. Test., 2009

Execution time reduction of Differential Power Analysis experiments.

[BibT_eX]

[DOI]

Proceedings of the 10th Latin American Test Workshop, 2009

2008

March Test Generation Revealed.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2008

A Modular Memory BIST for Optimized Memory Repair.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

A Reliable Architecture for the Advanced Encryption Standard.

[BibT_eX]

[DOI]

Proceedings of the 13th European Test Symposium, 2008

An Integrated Validation Environment for Differential Power Analysis.

[BibT_eX]

[DOI]

Proceedings of the 4th IEEE International Symposium on Electronic Design, 2008

On-Line Instruction-Checking in Pipelined Microprocessors.

[BibT_eX]

[DOI]

Stefano Di Carlo

Riccardo Mariani

Proceedings of the 17th IEEE Asian Test Symposium, 2008

LIFTING: A Flexible Open-Source Fault Simulator.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE Asian Test Symposium, 2008

2007

March AB, a state-of-the-art march test for realistic static linked faults and dynamic faults in SRAMs.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2007

A Dependable Parallel Architecture for SBoxes.

[BibT_eX]

Proceedings of the 3rd International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2007

An On-Line Fault Detection Scheme for SBoxes in Secure Circuits.

[BibT_eX]

[DOI]

Mohammad Hossein Neishaburi

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Analysis of System-Failure Rate Caused by Soft-Errors using a UML-Based Systematic Methodology in an SoC.

[BibT_eX]

[DOI]

Mohammad Hosseinabady

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

A Novel Parity Bit Scheme for SBox in AES Circuits.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2007), 2007

2006

Single-Event Upset Analysis and Protection in High Speed Circuits.

[BibT_eX]

[DOI]

Mohammad Hosseinabady

Proceedings of the 11th European Test Symposium, 2006

A 22n March Test for Realistic Static Linked Faults in SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 11th European Test Symposium, 2006

Automatic March Tests Generation for Multi-Port SRAMs.

[BibT_eX]

[DOI]

Proceedings of the Third IEEE International Workshop on Electronic Design, 2006

A Unique March Test Algorithm for the Wide Spread of Realistic Memory Faults in SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006

Automatic march tests generations for static linked faults in SRAMs.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2006

ATPG for Dynamic Burn-In Test in Full-Scan Circuits.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

Memory Fault Simulator for Static-Linked Faults.

[BibT_eX]

[DOI]

Proceedings of the 15th Asian Test Symposium, 2006

2005

March AB, March AB1: new March tests for unlinked dynamic memory faults.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2005 IEEE International Test Conference, 2005

Automatic March tests generation for static and dynamic faults in SRAMs.

[BibT_eX]

[DOI]

Proceedings of the 10th European Test Symposium, 2005

2003

Software-implemented system dependability for safety critical applications.

[BibT_eX]

[DOI]

PhD thesis, 2003

Online Self-Repair of FIR Filters.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2003

Programmable built-in self-testing of embedded RAM clusters in system-on-chip architectures.

[BibT_eX]

[DOI]

IEEE Commun. Mag., 2003

Data Critically Estimation In Software Applications.

[BibT_eX]

[DOI]

Proceedings of the Proceedings 2003 International Test Conference (ITC 2003), Breaking Test Interface Bottlenecks, 28 September, 2003

FAUST: FAUlt-injection Script-based Tool.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

A Watchdog Processor to Detect Data and Control Flow Errors.

[BibT_eX]

[DOI]

Proceedings of the 9th IEEE International On-Line Testing Symposium (IOLTS 2003), 2003

Exhaustive Test of Several Dependable Memory Architectures Designed by GRAAL Tool.

[BibT_eX]

[DOI]

Proceedings of the 12th Asian Test Symposium (ATS 2003), 17-19 November 2003, Xian, China, 2003

2002

An on-line BIST RAM architecture with self-repair capabilities.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2002

Static Analysis of SEU Effects on Software Applications.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2002, 2002

An Optimal Algorithm for the Automatic Generation of March Tests.

[BibT_eX]

[DOI]

Proceedings of the 2002 Design, 2002

Specification and Design of a New Memory Fault Simulator.

[BibT_eX]

[DOI]

Proceedings of the 11th Asian Test Symposium (ATS 2002), 18-20 November 2002, Guam, USA, 2002

2001

Online and Offline BIST in IP-Core Design.

[BibT_eX]

[DOI]

IEEE Des. Test Comput., 2001

GRAAL: a tool for highly dependable SRAMs generation.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2001, Baltimore, MD, USA, 30 October, 2001

Validation of a Software Dependability Tool via Fault Injection Experiments.

[BibT_eX]

[DOI]

Proceedings of the 7th IEEE International On-Line Testing Workshop (IOLTW 2001), 2001

SEU effect analysis in an open-source router via a distributed fault injection environment.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

Control-Flow Checking via Regular Expressions.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

Memory Read Faults: Taxonomy and Automatic Test Generation.

[BibT_eX]

[DOI]

Proceedings of the 10th Asian Test Symposium (ATS 2001), 19-21 November 2001, Kyoto, Japan, 2001

2000

A programmable BIST architecture for clusters of multiple-port SRAMs.

[BibT_eX]

[DOI]

Proceedings of the Proceedings IEEE International Test Conference 2000, 2000

A Family of Self-Repair SRAM Cores.

[BibT_eX]

[DOI]

Proceedings of the 6th IEEE International On-Line Testing Workshop (IOLTW 2000), 2000

An effective distributed BIST architecture for RAMs.

[BibT_eX]

[DOI]