Giorgio Cesana

According to our database, Giorgio Cesana authored at least 4 papers between 2013 and 2016.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2016

Low power advanced digital technologies to enable Internet of Things.

Laurent Malier, Andreia Cathelin, Giorgio Cesana, Laurent Le Pailleur

Proceedings of the 46th European Solid-State Device Research Conference, 2016

2014

A 3 GHz Dual Core Processor ARM Cortex TM -A9 in 28 nm UTBB FD-SOI CMOS With Ultra-Wide Voltage Range and Energy Efficiency Optimization.

David Jacquet, Frederic Hasbani, Philippe Flatresse, Robin Wilson, Franck Arnaud, Giorgio Cesana, Thierry Di Gilio, Christophe Lecocq, Tanmoy Roy, Amit Chhabra, Chiranjeev Grover, Olivier Minez, Jacky Uginet, Guy Durieu, Cyril Adobati, Davide Casalotto, Frederic Nyer, Patrick Menut, Andreia Cathelin, Indavong Vongsavady, Philippe Magarshack

IEEE J. Solid State Circuits, 2014

2013

Ultra-wide body-bias range LDPC decoder in 28nm UTBB FDSOI technology.

Philippe Flatresse, Bastien Giraud, Jean-Philippe Noel, Bertrand Pelloux-Prayer, Fabien Giner, Deepak-Kumar Arora, Franck Arnaud, Nicolas Planes, Julien Le Coz, Olivier Thomas, Sylvain Engels, Giorgio Cesana, Robin Wilson, Pascal Urard

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

UTBB FD-SOI: a process/design symbiosis for breakthrough energy-efficiency.

Philippe Magarshack, Philippe Flatresse, Giorgio Cesana

Proceedings of the Design, Automation and Test in Europe, 2013