Gilson I. Wirth
Orcid: 0000-0002-4990-5113
According to our database1,
Gilson I. Wirth
authored at least 60 papers
between 2000 and 2023.
Collaborative distances:
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Bibliography
2023
IEEE Trans. Circuits Syst. I Regul. Pap., 2023
2021
Modeling and Simulation of Charge Trapping in 1/f Noise, RTN and BTI: from Devices to Circuits.
Proceedings of the 2021 28th International Conference on Mixed Design of Integrated Circuits and System, 2021
2020
Microelectron. J., 2020
2018
Microelectron. Reliab., 2018
Microelectron. J., 2018
Design Flow Methodology for Radiation Hardened by Design CMOS Enclosed-Layout-Transistor-Based Standard-Cell Library.
J. Electron. Test., 2018
Time domain electrical characterization in zinc oxide nanoparticle thin-film transistors.
Proceedings of the 19th IEEE Latin-American Test Symposium, 2018
2017
Proceedings of the IEEE AFRICON 2017, Cape Town, South Africa, September 18-20, 2017, 2017
2016
Rail to rail radiation hardened operational amplifier in standard CMOS technology with standard layout techniques.
Microelectron. Reliab., 2016
MagPDK: An open-source process design kit for circuit design with magnetic tunnel junctions.
Proceedings of the 29th Symposium on Integrated Circuits and Systems Design, 2016
2015
Microelectron. Reliab., 2015
Microelectron. Reliab., 2015
Impact of Total Ionizing Dose on Bulk Built-In Current Sensors with Dynamic Storage Cell.
J. Electron. Test., 2015
Proceedings of the IEEE 6th Latin American Symposium on Circuits & Systems, 2015
Impact of dynamic voltage scaling and thermal factors on FinFET-based SRAM reliability.
Proceedings of the 2015 IEEE International Conference on Electronics, 2015
2014
IEEE Trans. Very Large Scale Integr. Syst., 2014
Low temperature fabrication of a ZnO nanoparticle thin-film transistor suitable for flexible electronics.
Microelectron. Reliab., 2014
Microelectron. Reliab., 2014
Microelectron. Reliab., 2014
Proceedings of the 15th Latin American Test Workshop, 2014
The effects of total ionizing dose on the neutron SEU cross section of a 130 nm 4 Mb SRAM memory.
Proceedings of the 15th Latin American Test Workshop, 2014
Aging and voltage scaling impacts under neutron-induced soft error rate in SRAM-based FPGAs.
Proceedings of the 19th IEEE European Test Symposium, 2014
2013
Proceedings of the 4th IEEE Latin American Symposium on Circuits and Systems, 2013
2012
Compact modeling and simulation of Random Telegraph Noise under non-stationary conditions in the presence of random dopants.
Microelectron. Reliab., 2012
Proceedings of the 25th Symposium on Integrated Circuits and Systems Design, 2012
2011
Microelectron. Reliab., 2011
Statistical characterization of standard cells using design of experiments with response surface modeling.
Proceedings of the 48th Design Automation Conference, 2011
Proceedings of the AFRICON 2011, 2011
2010
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
Design methodology using inversion coefficient for low-voltage low-power CMOS voltage reference.
Proceedings of the 23rd Annual Symposium on Integrated Circuits and Systems Design, 2010
2009
Proceedings of the 22st Annual Symposium on Integrated Circuits and Systems Design: Chip on the Dunes, 2009
Proceedings of the 10th Latin American Test Workshop, 2009
Using Bulk Built-In Current Sensors and recomputing techniques to mitigate transient faults in microprocessors.
Proceedings of the 10th Latin American Test Workshop, 2009
Measuring the effectiveness of symmetric and asymmetric transistor sizing for Single Event Transient mitigation in CMOS 90nm technologies.
Proceedings of the 10th Latin American Test Workshop, 2009
An experimental 0.6-V 57.5-fJ/conversion-step 250-kS/s 8-bit rail-to-rail successive approximation ADC in 0.18µm CMOS.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
2008
IEEE Trans. Circuits Syst. I Regul. Pap., 2008
Modeling the sensitivity of CMOS circuits to radiation induced single event transients.
Microelectron. Reliab., 2008
Bulk built in current sensors for single event transient detection in deep-submicron technologies.
Microelectron. Reliab., 2008
J. Electron. Test., 2008
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
"The flipped voltage follower"-based low voltage fully differential CMOS sample-and-hold circuit.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008
2007
Técnicas probabilísticas para análise de yield em nível elétrico usando propagação de erros e derivadas numéricas.
RITA, 2007
Accurate and computer efficient modelling of single event transients in CMOS circuits.
IET Circuits Devices Syst., 2007
Statistical Analysis of Normality of Systematic and Random Variability of Flip-Flop Race Immunity in 130nm and 90nm CMOS Technologies.
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007
Statistical analysis of systematic and random variability of flip-flop race immunity in 130nm and 90nm CMOS technologies.
Proceedings of the IFIP VLSI-SoC 2007, 2007
Proceedings of the VLSI-SoC: Advanced Topics on Systems on a Chip, 2007
Obtaining delay distribution of dynamic logic circuits by error propagation at the electrical level.
Proceedings of the IFIP VLSI-SoC 2007, 2007
A built-in current sensor for high speed soft errors detection robust to process and temperature variations.
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Proceedings of the 20th Annual Symposium on Integrated Circuits and Systems Design, 2007
Using built-in sensors to cope with long duration transient faults in future technologies.
Proceedings of the 2007 IEEE International Test Conference, 2007
Yield Analysis by Error Propagation Using Numerical Derivatives Considering WD and D2D variations.
Proceedings of the 2007 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2007), 2007
Proceedings of the International Symposium on System-on-Chip, 2007
Proceedings of the 14th IEEE International Conference on Electronics, 2007
2006
Proceedings of the 19th Annual Symposium on Integrated Circuits and Systems Design, 2006
Proceedings of the 9th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2006), 2006
2005
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
Evaluating fault coverage of bulk built-in current sensor for soft errors in combinational and sequential logic.
Proceedings of the 18th Annual Symposium on Integrated Circuits and Systems Design, 2005
2000
Digital Circuit Design Based on the Resonant-Tunneling-Hetero-Junction-Bipolar-Transistor.
Proceedings of the 13th Annual Symposium on Integrated Circuits and Systems Design, 2000