Gilles Festes
According to our database1,
Gilles Festes
authored at least 6 papers
between 2010 and 2024.
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Bibliography
2024
Performance and Reliability of Technology Qualified 34 Mb Split-Gate eFLASH Macro in 28 nm HKMG.
Proceedings of the IEEE International Memory Workshop, 2024
2023
Analog Tuning of Floating-Gate Cells with Sub-Elementary Charge Accuracy for In-Memory Computing Applications.
Proceedings of the IEEE International Memory Workshop, 2023
Effect of High-Temperature Bake on RTN Statistics in Floating Gate Flash Memory Arrays.
Proceedings of the IEEE International Memory Workshop, 2023
2012
Analysis and Fault Modeling of Actual Resistive Defects in ATMEL TSTAC<sup>TM</sup> eFlash Memories.
J. Electron. Test., 2012
2011
Proceedings of the 14th IEEE International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2011
2010
A two-layer SPICE model of the ATMEL TSTAC<sup>TM</sup> eFlash memory technology for defect injection and faulty behavior prediction.
Proceedings of the 15th European Test Symposium, 2010