Gianna Paulin

According to our database, Gianna Paulin authored at least 13 papers between 2017 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of three.

2024

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC With 2-8 b DNN Acceleration and 30%-Boost Adaptive Body Biasing.

Francesco Conti, Gianna Paulin, Angelo Garofalo, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini

IEEE J. Solid State Circuits, January, 2024

Occamy: A 432-Core 28.1 DP-GFLOP/s/W 83% FPU Utilization Dual-Chiplet, Dual-HBM2E RISC-V-Based Accelerator for Stencil and Sparse Linear Algebra Computations with 8-to-64-bit Floating-Point Support in 12nm FinFET.

Gianna Paulin, Paul Scheffler, Thomas Benz, Matheus A. Cavalcante, Tim Fischer, Manuel Eggimann, Yichao Zhang, Nils Wistoff, Luca Bertaccini, Luca Colagrande, Gianmarco Ottavi, Frank K. Gürkaynak, Davide Rossi, Luca Benini

Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024

2023

Marsellus: A Heterogeneous RISC-V AI-IoT End-Node SoC with 2-to-8b DNN Acceleration and 30%-Boost Adaptive Body Biasing.

Francesco Conti, Gianna Paulin, Davide Rossi, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Luca Benini

CoRR, 2023

A 12.4TOPS/W @ 136GOPS AI-IoT System-on-Chip with 16 RISC-V, 2-to-8b Precision-Scalable DNN Acceleration and 30%-Boost Adaptive Body Biasing.

Francesco Conti, Davide Rossi, Gianna Paulin, Angelo Garofalo, Alfio Di Mauro, Georg Rutishauser, Gianmarco Ottavi, Manuel Eggimann, Hayate Okuhara, Vincent Huard, Olivier Montfort, Lionel Jure, Nils Exibard, Pascal Gouedo, Mathieu Louvat, Emmanuel Botte, Luca Benini

Proceedings of the IEEE International Solid- State Circuits Conference, 2023

ITA: An Energy-Efficient Attention and Softmax Accelerator for Quantized Transformers.

Gamze Islamoglu, Moritz Scherer, Gianna Paulin, Tim Fischer, Victor J. B. Jung, Angelo Garofalo, Luca Benini

Proceedings of the IEEE/ACM International Symposium on Low Power Electronics and Design, 2023

PetaOps/W edge-AI $\mu$ Processors: Myth or reality?

Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Friedemann Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, Sam Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2023

2022

Vau Da Muntanialas: Energy-Efficient Multi-Die Scalable Acceleration of RNN Inference.

Gianna Paulin, Francesco Conti, Lukas Cavigelli, Luca Benini

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

CONVOLVE: Smart and seamless design of smart edge processors.

Manil Dev Gomony, Floran de Putter, Anteneh Gebregiorgis, Gianna Paulin, Linyan Mei, Vikram Jain, Said Hamdioui, Victor Sanchez, Tobias Grosser, Marc Geilen, Marian Verhelst, Frank K. Zenke, Frank K. Gürkaynak, Barry de Bruin, Sander Stuijk, Simon Davidson, Sayandip De, Mounir Ghogho, Alexandra Jimborean, Sherif Eissa, Luca Benini, Dimitrios Soudris, Rajendra Bishnoi, S. Ainsworth, Federico Corradi, Ouassim Karrakchou, Tim Güneysu, Henk Corporaal

CoRR, 2022

Soft Tiles: Capturing Physical Implementation Flexibility for Tightly-Coupled Parallel Processing Clusters.

Gianna Paulin, Matheus A. Cavalcante, Paul Scheffler, Luca Bertaccini, Yichao Zhang, Frank K. Gürkaynak, Luca Benini

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

MiniFloat-NN and ExSdotp: An ISA Extension and a Modular Open Hardware Unit for Low-Precision Training on RISC-V Cores.

Luca Bertaccini, Gianna Paulin, Tim Fischer, Stefan Mach, Luca Benini

Proceedings of the 29th IEEE Symposium on Computer Arithmetic, 2022

2021

RNN-Based Radio Resource Management on Multicore RISC-V Accelerator Architectures.

Gianna Paulin, Renzo Andri, Francesco Conti, Luca Benini

IEEE Trans. Very Large Scale Integr. Syst., 2021

2018

Chipmunk: A systolically scalable 0.9 mm², 3.08Gop/s/mW @ 1.2 mW accelerator for near-sensor recurrent neural network inference.

Francesco Conti, Lukas Cavigelli, Gianna Paulin, Igor Susmelj, Luca Benini

Proceedings of the 2018 IEEE Custom Integrated Circuits Conference, 2018

2017

Chipmunk: A Systolically Scalable 0.9 mm², 3.08 Gop/s/mW @ 1.2 mW Accelerator for Near-Sensor Recurrent Neural Network Inference.

Francesco Conti, Lukas Cavigelli, Gianna Paulin, Igor Susmelj, Luca Benini

CoRR, 2017