Gianluca Piccinini

According to our database, Gianluca Piccinini authored at least 52 papers between 1987 and 2023.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2023

Design of Pyrrole-Based Gate-Controlled Molecular Junctions Optimized for Single-Molecule Aflatoxin B1 Detection.

Fabrizio Mo, Chiara Elfi Spano, Yuri Ardesi, Massimo Ruo Roch, Gianluca Piccinini, Mariagrazia Graziano

Sensors, February, 2023

Taming Molecular Field-Coupling for Nanocomputing Design.

Yuri Ardesi, Umberto Garlando, Fabrizio Riente, Giuliana Beretta, Gianluca Piccinini, Mariagrazia Graziano

ACM J. Emerg. Technol. Comput. Syst., January, 2023

Advances in Modeling of Noisy Quantum Computers: Spin Qubits in Semiconductor Quantum Dots.

Davide Costa, Mario Simoni, Gianluca Piccinini, Mariagrazia Graziano

IEEE Access, 2023

2021

SCERPA Simulation of Clocked Molecular Field-Coupling Nanocomputing.

Yuri Ardesi, Giovanna Turvani, Mariagrazia Graziano, Gianluca Piccinini

IEEE Trans. Very Large Scale Integr. Syst., 2021

A Reconfigurable Field-Coupled Nanocomputing Paradigm on Uniform Molecular Monolayers.

Yuri Ardesi, Giuliana Beretta, Christian Fabiano, Mariagrazia Graziano, Gianluca Piccinini

Proceedings of the 2021 International Conference on Rebooting Computing (ICRC), Los Alamitos, CA, USA, November 30, 2021

2020

SCERPA: A Self-Consistent Algorithm for the Evaluation of the Information Propagation in Molecular Field-Coupled Nanocomputing.

Yuri Ardesi, Ruiyu Wang, Giovanna Turvani, Gianluca Piccinini, Mariagrazia Graziano

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019

Bistable Propagation of Monostable Molecules in Molecular Field-Coupled Nanocomputing.

Yuri Ardesi, Luca Gnoli, Mariagrazia Graziano, Gianluca Piccinini

Proceedings of the 15th Conference on Ph.D. Research in Microelectronics and Electronics, 2019

2018

Nanoarrays for Systolic Biosequence Analysis.

Malik Ashter Mehdy, Aleandro Antidormi, Mariagrazia Graziano, Gianluca Piccinini

J. Circuits Syst. Comput., 2018

2015

Result-Biased Distributed-Arithmetic-Based Filter Architectures for Approximately Computing the DWT.

Maurizio Martina, Guido Masera, Massimo Ruo Roch, Gianluca Piccinini

IEEE Trans. Circuits Syst. I Regul. Pap., 2015

Process Variability and Electrostatic Analysis of Molecular QCA.

Mariagrazia Graziano, Azzurra Pulimeno, Ruiyu Wang, Xiang Wei, Massimo Ruo Roch, Gianluca Piccinini

ACM J. Emerg. Technol. Comput. Syst., 2015

2014

Understanding a Bisferrocene Molecular QCA Wire.

Azzurra Pulimeno, Mariagrazia Graziano, Aleandro Antidormi, Ruiyu Wang, Ali Zahir, Gianluca Piccinini

Proceedings of the Field-Coupled Nanocomputing - Paradigms, Progress, and Perspectives, 2014

A Parallel Radix-Sort-Based VLSI Architecture for Finding the First W Maximum/Minimum Values.

Guoping Xiao, Maurizio Martina, Guido Masera, Gianluca Piccinini

IEEE Trans. Circuits Syst. II Express Briefs, 2014

Variable Parallelism Cyclic Redundancy Check Circuit for 3GPP-LTE/LTE-Advanced.

Carlo Condo, Maurizio Martina, Gianluca Piccinini, Guido Masera

IEEE Signal Process. Lett., 2014

Molecular transistor circuits: From device model to circuit simulation.

Ali Zahir, Syed Azhar Ali Zaidi, Azzurra Pulimeno, Mariagrazia Graziano, Danilo Demarchi, Guido Masera, Gianluca Piccinini

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2014

2013

Charge distribution in a molecular QCA wire based on bis-ferrocene molecules.

Azzurra Pulimeno, Mariagrazia Graziano, Ruiyu Wang, Danilo Demarchi, Gianluca Piccinini

Proceedings of the IEEE/ACM International Symposium on Nanoscale Architectures, 2013

Nanogap-based enzymatic-free electrochemical detection of glucose.

Ismael Rattalino, Paolo Motto Ros, Irene Taurino, Fernando Cortes-Salazar, Gianluca Piccinini, Danilo Demarchi, Giovanni De Micheli, Sandro Carrara

Proceedings of the 2013 IEEE Biomedical Circuits and Systems Conference (BioCAS), Rotterdam, The Netherlands, October 31, 2013

2012

UDSM Trends Comparison: From Technology Roadmap to UltraSparc Niagara2.

Azzurra Pulimeno, Mariagrazia Graziano, Gianluca Piccinini

IEEE Trans. Very Large Scale Integr. Syst., 2012

2010

Scalable low-complexity B-spline discrete wavelet transform architecture.

Maurizio Martina, Guido Masera, Gianluca Piccinini

IET Circuits Devices Syst., 2010

2008

Statistical power supply dynamic noise prediction in hierarchical power grid and package networks.

Mariagrazia Graziano, Gianluca Piccinini

Integr., 2008

2004

An electromigration and thermal model of power wires for a priori high-level reliability prediction.

Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni

IEEE Trans. Very Large Scale Integr. Syst., 2004

Effects of temperature in deep-submicron global interconnect optimization in future technology nodes.

Mariagrazia Graziano, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni

Microelectron. J., 2004

2003

Novel JPEG 2000 Compliant DWT and IWT VLSI Implementations.

Maurizio Martina, Guido Masera, Gianluca Piccinini, Maurizio Zamboni

J. VLSI Signal Process., 2003

Coupled electro-thermal modeling and optimization of clock networks.

Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni

Microelectron. J., 2003

Effects of Temperature in Deep-Submicron Global Interconnect Optimization.

Mario R. Casu, Mariagrazia Graziano, Gianluca Piccinini, Guido Masera, Maurizio Zamboni

Proceedings of the Integrated Circuit and System Design, 2003

A Block-Based Approach for SoC Global Interconnect Electrical Parameters Characterization.

M. Addino, Mario R. Casu, Guido Masera, Gianluca Piccinini, Maurizio Zamboni

Proceedings of the Integrated Circuit and System Design, 2003

Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding.

Federico Quaglio, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Molino, Gianluca Piccinini, Maurizio Zamboni

Proceedings of the ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2003

2002

Architectural strategies for low-power VLSI turbo decoders.

Guido Masera, Marco Mazza, Gianluca Piccinini, Fabrizio Viglione, Maurizio Zamboni

IEEE Trans. Very Large Scale Integr. Syst., 2002

Clock Distribution Network Optimization under Self-Heating and Timing Constraints.

Mario R. Casu, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, M. M. Prono, Maurizio Zamboni

Proceedings of the Integrated Circuit Design. Power and Timing Modeling, 2002

Embedded IWT evaluation in reconfigurable wireless sensor network.

Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

System architecture for error-resilient, embedded JPEG2000 wireless delivery.

Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni

Proceedings of the 14th International Conference on Digital Signal Processing, 2002

Reconfigurable DSP IP for multimedia applications.

Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni

Proceedings of the IEEE International Conference on Acoustics, 2002

Energy Evaluation on a Reconfigurable, Multimedia-Oriented Wireless Sensor.

Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni

Proceedings of the Field-Programmable Logic and Applications, 2002

2001

Switching Noise Analysis Framework For High Speed Logic Families.

Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni

Proceedings of the 14th International Conference on VLSI Design (VLSI Design 2001), 2001

Hierarchical power supply noise evaluation for early power grid design prediction.

Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni

Proceedings of the Third IEEE/ACM International Workshop on System-Level Interconnect Prediction (SLIP 2001), March 31, 2001

Synthesis of low-leakage PD-SOI circuits with body-biasing.

Mario R. Casu, Gianluca Piccinini, Guido Masera, Maurizio Zamboni

Proceedings of the 2001 International Symposium on Low Power Electronics and Design, 2001

Reconfigurable coprocessor based JPEG 2000 implementation.

Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

JPEG 2000: finite precision representation and hardware implications.

Maurizio Martina, Guido Masera, Gianluca Piccinini, Fabrizio Vacca, Maurizio Zamboni

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

2000

Noise Safety Design Methodologies.

Mariagrazia Graziano, Marco Delaurenti, Guido Masera, Gianluca Piccinini, Maurizio Zamboni

Proceedings of the 1st International Symposium on Quality of Electronic Design (ISQED 2000), 2000

A high accuracy-low complexity model for CMOS delays.

Mario Roberto Casu, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A 50 Mbit/s Iterative Turbo-Decoder.

Fabrizio Viglione, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni

Proceedings of the 2000 Design, 2000

1999

VLSI architectures for turbo codes.

Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni

IEEE Trans. Very Large Scale Integr. Syst., 1999

A global optimization tool for CMOS logic circuits.

Marco Delaurenti, Mariagrazia Graziano, Guido Masera, Gianluca Piccinini, Maurizio Zamboni

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

New 2 Gbit/s CMOS I/O pads.

Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni

Proceedings of the 9th Great Lakes Symposium on VLSI (GLS-VLSI '99), 1999

A Quantitative Approach to the Design of an Optimized Hardware Interpreter for Java Byte-Code.

Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni

Proceedings of the 17th IASTED International Conference on Applied Informatics, 1999

1998

Fanout optimization under a submicron transistor-level delay model.

Pasquale Cocchini, Massoud Pedram, Gianluca Piccinini, Maurizio Zamboni

Proceedings of the 1998 IEEE/ACM International Conference on Computer-Aided Design, 1998

A 500 MHz 2d-DWT VLSI processor.

A. Brizio, Guido Masera, Gianluca Piccinini, Massimo Ruo Roch, Maurizio Zamboni

Proceedings of the 9th European Signal Processing Conference, 1998

1997

A comprehensive submicrometer MOST delay model and its application to CMOS buffers.

Pasquale Cocchini, Gianluca Piccinini, Maurizio Zamboni

IEEE J. Solid State Circuits, 1997

1996

A 650 MHz pipelined MAC for DSP applications using a new clocking strategy.

F. Fraternali, Guido Masera, Gianluca Piccinini, Maurizio Zamboni

Proceedings of the 8th European Signal Processing Conference, 1996

1992

Deflection network: Principles, implementation, services.

Guido Albertengo, Pierluigi Civera, Renato Lo Cigno, Gianluca Piccinini, Maurizio Zamboni, Flaminio Borgonovo, Luigi Fratta, Giuseppe Panizzardi

Eur. Trans. Telecommun., 1992

1989

Implementation studies for a VLSI Prolog coprocessor.

Pierluigi Civera, Gianluca Piccinini, Maurizio Zamboni

IEEE Micro, 1989

1987

Design considerations on a VLSI Prolog interpreter.

Pierluigi Civera, Gianluca Piccinini, Maurizio Zamboni

Microprocess. Microprogramming, 1987

An Experimental VLSI Prolog Interpreter: Preliminary Measurements and Results.

Pierluigi Civera, Franco Maddaleno, Gianluca Piccinini, Maurizio Zamboni

Proceedings of the 14th Annual International Symposium on Computer Architecture. Pittsburgh, 1987