Gian Carlo Cardarilli

Seok-Bum Ko

Nano Commun. Networks, 2024

A Novel Digital Equalizer Based on RF Sampling Beyond GHz.

[BibT_eX]

[DOI]

IEEE Access, 2024

Design Space Exploration for Edge Machine Learning Featured by MathWorks FPGA DL Processor: A Survey.

[BibT_eX]

[DOI]

Stefano Bertazzoni

IEEE Access, 2024

2023

Efficient Digital Implementation of a Multirate-Based Variable Fractional Delay Filter for Wideband Beamforming.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, June, 2023

A Survey on Deep Learning Hardware Accelerators for Heterogeneous HPC Platforms.

[BibT_eX]

[DOI]

CoRR, 2023

An RNS-Based Initial Absolute Position Estimator for Electrical Encoders.

[BibT_eX]

[DOI]

IEEE Access, 2023

A RISC-V Hardware Accelerator for Q-Learning Algorithm.

[BibT_eX]

[DOI]

Damiano Angeloni

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023

Tunable Floating Point for High Quality Audio Systems: The Sound of Numbers.

[BibT_eX]

[DOI]

Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

A Hardware-Oriented QAM Demodulation Method Driven by AW-SOM Machine Learning.

[BibT_eX]

[DOI]

Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

2022

Design Space Exploration Based Methodology for Residue Number System Digital Filters Implementation.

[BibT_eX]

[DOI]

IEEE Trans. Emerg. Top. Comput., 2022

Sensing and Detection of Traffic Signs Using CNNs: An Assessment on Their Performance.

[BibT_eX]

[DOI]

Hamed Famil Ghadakchi

Sensors, 2022

An FPGA-based multi-agent Reinforcement Learning timing synchronizer.

[BibT_eX]

[DOI]

Comput. Electr. Eng., 2022

FPGA-Based Road Crack Detection Using Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the Advances in System-Integrated Intelligence, 2022

Profiling of CNNs using the MATLAB FPGA-based Deep Learning Processor.

[BibT_eX]

[DOI]

Proceedings of the 17th Conference on Ph.D Research in Microelectronics and Electronics, 2022

AI-Based Sound Event Detection on IoT Nodes: Requirements Evaluation.

[BibT_eX]

[DOI]

D. Errico

V. Colombo

M. Martina

M. Ruo Roch

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022

Automatic IP Core Generator for FPGA-Based Q-Learning Hardware Accelerators.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022

2021

M-PSK Demodulator With Joint Carrier and Timing Recovery.

[BibT_eX]

[DOI]

Daniele Giardino

IEEE Trans. Circuits Syst. II Express Briefs, 2021

A Parallel Hardware Implementation for 2-D Hierarchical Clustering Based on Fuzzy Logic.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2021

Design and FPGA Implementation of a Low Power OFDM Transmitter for Narrow-Band IoT.

[BibT_eX]

[DOI]

Proceedings of the Scholar's Yearly Symposium of Technology, 2021

A M-PSK Timing Recovery Loop Based on Q-Learning.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2021

"MR Q-Learning" Algorithm for Efficient Hardware Implementations.

[BibT_eX]

[DOI]

Proceedings of the 55th Asilomar Conference on Signals, Systems, and Computers, 2021

2020

AW-SOM, an Algorithm for High-Speed Learning in Hardware Self-Organizing Maps.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

N-Dimensional Approximation of Euclidean Distance.

[BibT_eX]

[DOI]

IEEE Trans. Circuits Syst. II Express Briefs, 2020

An Action-Selection Policy Generator for Reinforcement Learning Hardware Accelerators.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2020

FPGA Implementation of Q-RTS for Real-Time Swarm Intelligence Systems.

[BibT_eX]

[DOI]

Proceedings of the 54th Asilomar Conference on Signals, Systems, and Computers, 2020

2019

An Efficient Hardware Implementation of Reinforcement Learning: The Q-Learning Algorithm.

[BibT_eX]

[DOI]

IEEE Access, 2019

A Reinforcement Learning-Based QAM/PSK Symbol Synchronizer.

[BibT_eX]

[DOI]

Marco Matta

IEEE Access, 2019

Digital Signal Processing Accelerator for RISC-V.

[BibT_eX]

[DOI]

L. Calicchia

V. Ciotoli

Proceedings of the 26th IEEE International Conference on Electronics, Circuits and Systems, 2019

Acoustic Emissions Detection and Ranging of Cracks in Metal Tanks Using Deep Learning.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2019

Approximated Canonical Signed Digit for Error Resilient Intelligent Computation.

[BibT_eX]

[DOI]

Amirhossein Fereidountabar

Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2018

Channel estimation for high speed unmanned aerial vehicle with STBC in MIMO radio links.

[BibT_eX]

[DOI]

Int. J. Comput. Vis. Robotics, 2018

Digital Architecture and ASIC Implementation of Wideband Delta DOR Spacecraft Onboard Tracker.

[BibT_eX]

[DOI]

Proceedings of the 15th International Conference on Synthesis, 2018

Setup and experimental results analysis of COTS Camera and SRAMs at the ISIS neutron facility.

[BibT_eX]

[DOI]

Alessandro Scaramella

Simone Stramaccioni

Alessia Zibecchi

Carla Andreani

Proceedings of the 13th International Conference on Design & Technology of Integrated Systems In Nanoscale Era, 2018

Efficient Ensemble Machine Learning Implementation on FPGA Using Partial Reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

Comparison and Implementation of Variable Fractional Delay Filters for Wideband Digital Beamforming.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2018

A Power Efficient Digital Front-End for Cognitive Radio Systems.

[BibT_eX]

[DOI]

Proceedings of the 52nd Asilomar Conference on Signals, Systems, and Computers, 2018

2017

Hardware design of LIF with Latency neuron model with memristive STDP synapses.

[BibT_eX]

[DOI]

Integr., 2017

Robust throughput boosting for low latency dynamic partial reconfiguration.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE International System-on-Chip Conference, 2017

A new electric encoder position estimator based on the Chinese Remainder Theorem for the CMG performance improvements.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2017

FPGA Implementation of a Low-Power QRS Extractor.

[BibT_eX]

[DOI]

Francesca Silvestri

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2017

A Wireless Sensor Node for Acoustic Emission Non-destructive Testing.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2017

Digital Architecture of Next Generation Spacecraft Tracker Based on Wideband ∆DOR.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2017

2016

A hardware framework for on-chip FPGA acceleration.

[BibT_eX]

[DOI]

Andrea Lomuscio

Proceedings of the International Symposium on Integrated Circuits, 2016

Design and characterization of a high-safety hardware/software module for the acquisition of Eurobalise telegrams.

[BibT_eX]

[DOI]

Filippo Giuliani

Proceedings of the 2016 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2016

ZnO-rGO Composite Thin Film Resistive Switching Device: Emulating Biological Synapse Behavior.

[BibT_eX]

[DOI]

Gaurav Mani Khanal

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2016

Compressive Sensing Reconstruction for Complex System: A Hardware/Software Approach.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2016

Dynamically-loaded Hardware Libraries (HLL) technology for audio applications.

[BibT_eX]

[DOI]

A. Esposito

Andrea Lomuscio

Amirhossein Fereidountabar

Proceedings of the 50th Asilomar Conference on Signals, Systems and Computers, 2016

2015

High Dynamic Optimized Carrier Loop Improvement for Tracking Doppler Rates.

[BibT_eX]

[DOI]

J. Electr. Comput. Eng., 2015

Characterization of RNS multiply-add units for power efficient DSP.

[BibT_eX]

[DOI]

Proceedings of the IEEE 58th International Midwest Symposium on Circuits and Systems, 2015

A framework for dynamically-loaded hardware library (HLL) in FPGA acceleration.

[BibT_eX]

[DOI]

Leonardo Di Carlo

Federico Maria Pandolfi

Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2015

A Wireless Sensor Node Based on Microbial Fuel Cell.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2015

2014

Twenty years of research on RNS for DSP: Lessons learned and future perspectives.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Symposium on Integrated Circuits (ISIC), 2014

TDES cryptography algorithm acceleration using a reconfigurable functional unit.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014

2013

High Performance Bit-Stream Decompressor for Partial Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Ilir Shuli

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2013

A Reconfigurable Functional Unit for Modular Operations.

[BibT_eX]

[DOI]

Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2013

Compressive sensing spectrum analysis for space autonomous radio receivers.

[BibT_eX]

[DOI]

Ilir Shuli

Lorenzo Simone

Proceedings of the 2013 Asilomar Conference on Signals, 2013

Spiking neural networks based on LIF with latency: Simulation and synchronization effects.

[BibT_eX]

[DOI]

Proceedings of the 2013 Asilomar Conference on Signals, 2013

Truncated multipliers through power-gating for degrading precision arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 2013 Asilomar Conference on Signals, 2013

2012

Optimized Implementation of RNS FIR Filters Based on FPGAs.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2012

Power efficient design of parallel/serial FIR filters in RNS.

[BibT_eX]

[DOI]

Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

Integration of butterfly and inverse butterfly nets in embedded processors: Effects on power saving.

[BibT_eX]

[DOI]

Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

Karatsuba implementation of FIR filters.

[BibT_eX]

[DOI]

Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

Imprecise arithmetic for low power image processing.

[BibT_eX]

[DOI]

Proceedings of the Conference Record of the Forty Sixth Asilomar Conference on Signals, 2012

2011

Partial reconfiguration in the implementation of autonomous radio receivers for space.

[BibT_eX]

[DOI]

Ilir Shuli

Lorenzo Simone

Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Fine-grain Reconfigurable Functional Unit for embedded processors.

[BibT_eX]

[DOI]

Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011

2010

Algorithm acceleration on LEON-2 processor using a reconfigurable bit manipulation unit.

[BibT_eX]

[DOI]

Proceedings of the 8th Workshop on Intelligent Solutions in Embedded Systems, 2010

VLSI implementation of reconfigurable cells for RFU in embedded processors.

[BibT_eX]

[DOI]

Proceedings of the 17th IEEE International Conference on Electronics, 2010

2009

Improved Large-signal Model for Vacuum Triodes.

[BibT_eX]

[DOI]

Leonardo Di Carlo

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Speed-up of RISC Processor Computation using ADAPTO.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Arithmetic/Logic Blocks for Fine-grained Reconfigurable Units.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Error detection in addition chain based ECC Point Multiplication.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International On-Line Testing Symposium (IOLTS 2009), 2009

Error Correction Codes for SEU and SEFI Tolerant Memory Systems.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2009

2008

Describing Different Brain Computer Interface Systems Through a Unique Model: A UML Implementation.

[BibT_eX]

[DOI]

Lucia Rita Quitadamo

Maria Grazia Marciani

Luigi Bianchi

Neuroinformatics, 2008

Analysis and Evaluations of Reliability of Reconfigurable FPGAs.

[BibT_eX]

[DOI]

Vamsi Vankamamidi

Fabrizio Lombardi

J. Electron. Test., 2008

On the Comparison of Different Number Systems in the Implementation of Complex FIR Filters.

[BibT_eX]

[DOI]

Proceedings of the VLSI-SoC: Design Methodologies for SoC and SiP, 2008

ADAPTO: full-adder based reconfigurable architecture for bit level operations.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Totally Fault Tolerant RNS Based FIR Filters.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE International On-Line Testing Symposium (IOLTS 2008), 2008

On the use of signed digit arithmetic for the new 6-inputs LUT based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A full-adder based reconfigurable architecture for fine grain applications: ADAPTO.

[BibT_eX]

[DOI]

Proceedings of the 15th IEEE International Conference on Electronics, Circuits and Systems, 2008

A Novel Error Detection and Correction Technique for RNS Based FIR Filters.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2008), 2008

A Software Defined Radio Architecture for a Regenerative Onboard processor.

[BibT_eX]

[DOI]

Francesco Iacomacci

Catherine Morlet

Francesca Autelitano

Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008

Reducing power dissipation in pipelined accumulators.

[BibT_eX]

[DOI]

Proceedings of the 42nd Asilomar Conference on Signals, Systems and Computers, 2008

2007

Concurrent Error Detection in Reed-Solomon Encoders and Decoders.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Analysis of Errors and Erasures in Parity Sharing RS Codecs.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2007

Low-power adaptive filter based on RNS components.

[BibT_eX]

[DOI]

G. L. Bernocchi

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Self Checking Circuit Optimization by means of Fault Injection Analysis: A Case Study on Reed Solomon Decoders.

[BibT_eX]

[DOI]

Luca Sterpone

Proceedings of the 13th IEEE International On-Line Testing Symposium (IOLTS 2007), 2007

Optimization of Self Checking FIR filters by means of Fault Injection Analysis.

[BibT_eX]

[DOI]

Luca Sterpone

Proceedings of the 22nd IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2007), 2007

2006

Fault Localization, Error Correction, and Graceful Degradation in Radix 2 Signed Digit-Based Adders.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2006

Optimized QPSK modulator for DVB-S applications.

[BibT_eX]

[DOI]

Lorenzo Simone

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Fault tolerant design of signed digit based FIR filters.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Concurrent error detection in Reed Solomon decoders.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Localization of Faults in Radix-n Signed Digit Adders.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE International On-Line Testing Symposium (IOLTS 2006), 2006

2005

A Comparative Evaluation of Designs for Reliable Memory Systems.

[BibT_eX]

[DOI]

J. Electron. Test., 2005

Evaluating the Data Integrity of Memory Systems by Configurable Markov Models.

[BibT_eX]

[DOI]

Proceedings of the 2005 IEEE Computer Society Annual Symposium on VLSI (ISVLSI 2005), 2005

Programmable power-of-two RNS scaler and its application to a QRNS polyphase filter.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

Design of a Self Checking Reed Solomon Encoder.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE International On-Line Testing Symposium (IOLTS 2005), 2005

FPGA implementation of a general purpose HMM processor based on token passing algorithm.

[BibT_eX]

[DOI]

D. Bianchi

A. Malatesta

Proceedings of the 2005 European Conference on Circuit Theory and Design, 2005

FPGA oriented design of parity sharing RS codecs.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

A Self Checking Reed Solomon Encoder: Design and Analysis.

[BibT_eX]

[DOI]

Proceedings of the 20th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2005), 2005

2004

Low-power implementation of polyphase filters in Quadratic Residue Number system.

[BibT_eX]

Proceedings of the 2004 International Symposium on Circuits and Systems, 2004

A Signed Digit Adder with Error Correction and Graceful Degradation Capabilities.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE International On-Line Testing Symposium (IOLTS 2004), 2004

Data Integrity Evaluations of Reed Solomon Codes for Storage Systems.

[BibT_eX]

[DOI]

Proceedings of the 19th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2004), 2004

2003

Design of a fault tolerant solid state mass memory.

[BibT_eX]

[DOI]

IEEE Trans. Reliab., 2003

Power-delay tradeoffs in residue number system.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

IP based reconfigurable digital platform for satellite communications.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A fault tolerant hardware based file system manager for solid state mass memory.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Error Detection in Signed Digit Arithmetic Circuit with Parity Checker.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2003), 2003

2002

Efficient Implementation of a Demultiplexer Based on a Multirate Filter Bank for the Skyplex Satellites DVB System.

[BibT_eX]

[DOI]

VLSI Design, 2002

A self-checking cell logic block for fault tolerant FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Power characterization of digital filters implemented on FPGA.

[BibT_eX]

[DOI]

Proceedings of the 2002 International Symposium on Circuits and Systems, 2002

Bit Flip Injection in Processor-Based Architectures: A Case Study.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE International On-Line Testing Workshop (IOLTW 2002), 2002

2001

FPGA realization of RNS to binary signed conversion architecture.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Development of a dynamic routing system for a fault tolerant solid state mass memory.

[BibT_eX]

[DOI]

Panfilo Marinucci

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

Tradeoffs between residue number system and traditional FIR filters.

[BibT_eX]

[DOI]

Proceedings of the 2001 International Symposium on Circuits and Systems, 2001

System-on-Chip Oriented Fault-Tolerant Sequential Systems Implementation Methodology.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

Design of a Totally Self Checking Signature Analysis Checker for Finite State Machines.

[BibT_eX]

[DOI]

Proceedings of the 16th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2001), 2001

2000

A CAD environment for fuzzy systems HW/SW mapping.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

FPGA implementation of a demux based on a multirate filter bank.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Development of an evaluation model for the design of fault-tolerant solid state mass memory.

[BibT_eX]

[DOI]

Panfilo Marinucci

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

A novel bacterial algorithm to extract the rule base from a training set.

[BibT_eX]

[DOI]

Enrico Petrongari

Proceedings of the Ninth IEEE International Conference on Fuzzy Systems, 2000

A Fault-Tolerant 176 Gbit Solid State Mass Memory Architecture.

[BibT_eX]

[DOI]

P. Marinucci

Alberto L. Sangiovanni-Vincentelli

Proceedings of the 15th IEEE International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT 2000), 2000

1999

Analysis of the quantization noise effects on the SQNR behaviour in analog to digital conversion.

[BibT_eX]

[DOI]

Luciano Lavagno

Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999

Bipolar and CMOS low voltage-supply reduced-power voltage followers.

[BibT_eX]

[DOI]

Giuseppe Ferri

Franco Alfonsetti

Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999

Design of Fault-Tolerant Solid State Mass Memory.

[BibT_eX]

[DOI]

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

Failure Tests on 64 Mb SDRAM in Radiation Environment.

[BibT_eX]

[DOI]

Stefano Bertazzoni

D. Piergentili

Domenico Di Giovenale

Proceedings of the 14th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '99), 1999

1998

VLSI implementation of a real time fuzzy processor.

[BibT_eX]

[DOI]

J. Intell. Fuzzy Syst., 1998

1996

A low-voltage reduced-power constant-g<sub>m</sub> rail-to-rail fully differential CMOS op-amp.

[BibT_eX]

[DOI]

Giuseppe Ferri

Willy Sansen

Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996

1995

Analysis and implementation of a VLSI neural network.

[BibT_eX]

[DOI]

Gabriele Di Stefano

G. Fabrizi

P. Marinucci

Proceedings of International Conference on Neural Networks (ICNN'95), Perth, WA, Australia, November 27, 1995

1993

A High Speed Reed-Solomon Encoder-Decoder for Fault Tolerant Solid State Disks.

[BibT_eX]

M. Di Zenzo

Pat O. Pistilli

Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993

1992

Letter limit cycles in residue number system filters.

[BibT_eX]

[DOI]

Martin Hasler

Eur. Trans. Telecommun., 1992

Grid Generation and Verification for 3-D Device Simulation.

[BibT_eX]

Proceedings of the Eurosim 1992, Simulation Congress, Proceedings of the 1992 EUROSIM Conference, Capri, Italy, September 28, 1992

1990

RNS approach to full parallel linear combinators.

[BibT_eX]

[DOI]

Mario Salerno

F. Sargeni

Proceedings of the 1990 International Conference on Acoustics, 1990

1989

RNS approach to fast dividers.

[BibT_eX]

[DOI]

Mario Salerno

Proceedings of the IEEE International Conference on Acoustics, 1989

1988

RNS Fourier transforms.

[BibT_eX]

[DOI]

Pietro Burrascano