Giacomo Buonanno
According to our database1,
Giacomo Buonanno
authored at least 34 papers
between 1990 and 2021.
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Book In proceedings Article PhD thesis Dataset OtherLinks
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Bibliography
2021
Proceedings of the Human-Computer Interaction - INTERACT 2021 - 18th IFIP TC 13 International Conference, Bari, Italy, August 30, 2021
2011
Interorganisational systems within SMEs aggregations: an exploratory study on information requirements of an industrial district.
Int. J. Inf. Technol. Manag., 2011
2005
Factors affecting ERP system adoption: A comparative analysis between SMEs and large companies.
J. Enterp. Inf. Manag., 2005
Using Critical Success Factors for Assessing Critical Activities in ERP Implementation within SMEs.
Proceedings of the ICEIS 2005, 2005
Exploring the Role of Inter-Organizational Information Systems within SMEs Aggregations.
Proceedings of the 18th Bled eConference: eIntegration in Action, 2005
2000
J. Syst. Archit., 2000
ICT diffusion and strategic role within Italian SMEs.
Proceedings of the Challenges of Information Technology Management in the 21st Century, 2000
1998
Integr. Comput. Aided Eng., 1998
Proceedings of the 13th International Symposium on Defect and Fault-Tolerance in VLSI Systems (DFT '98), 1998
1997
Proceedings of the 15th IEEE VLSI Test Symposium (VTS'97), 1997
Application of a Testing Framework to VHDL Descriptions at Different Abstraction Levels.
Proceedings of the Proceedings 1997 International Conference on Computer Design: VLSI in Computers & Processors, 1997
Proceedings of the 7th Great Lakes Symposium on VLSI (GLS-VLSI '97), 1997
Proceedings of the 1997 Workshop on Defect and Fault-Tolerance in VLSI Systems (DFT '97), 1997
1996
Proceedings of the 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 1996
1995
Proceedings of the 8th International Conference on VLSI Design (VLSI Design 1995), 1995
Behavior of Self-Checking Checkers for 1-out-of-3 Codes Based on Pass-Transistor Logic.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
Data Path Testability Analysis Based on BDDs.
Proceedings of the 1995 IEEE International Symposium on Circuits and Systems, ISCAS 1995, Seattle, Washington, USA, April 30, 1995
1994
IEEE Trans. Very Large Scale Integr. Syst., 1994
IEEE Trans. Computers, 1994
Proceedings of the 1994 IEEE International Symposium on Circuits and Systems, ISCAS 1994, London, England, UK, May 30, 1994
A CMOS Fault Tolerant Architecture for Swith-Level Faults.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1994
1993
Proceedings of the Sixth International Conference on VLSI Design, 1993
An Expert Solution to Functional Testability Analysis of VLSI Circuits.
Proceedings of the SEKE'93, 1993
Functional Testing and Constrained Synthesis of Sequential Architectures.
Proceedings of the 1993 IEEE International Symposium on Circuits and Systems, 1993
Proceedings of the Proceedings 1993 International Conference on Computer Design: VLSI in Computers & Processors, 1993
Fault Detection in Sequential Circuits through Functional Testing.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks.
Proceedings of the IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, 1993
1992
Microprocess. Microprogramming, 1992
Proceedings of the conference on European design automation, 1992
1991
Microprocessing and Microprogramming, 1991
Proceedings of the conference on European design automation, 1991
1990
Microprocessing and Microprogramming, 1990