Giacomino Bollati
According to our database1,
Giacomino Bollati
authored at least 9 papers
between 1997 and 2020.
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Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2020
A 243-mW 1.25-56-Gb/s Continuous Range PAM-4 42.5-dB IL ADC/DAC-Based Transceiver in 7-nm FinFET.
IEEE J. Solid State Circuits, 2020
2019
A Sub-250mW 1-to-56Gb/s Continuous-Range PAM-4 42.5dB IL ADC/DAC-Based Transceiver in 7nm FinFET.
Proceedings of the IEEE International Solid- State Circuits Conference, 2019
2010
IEEE J. Solid State Circuits, 2010
Proceedings of the IEEE International Solid-State Circuits Conference, 2010
A 94dB-SNR -76dB-THD high-efficiency hybrid audio power-DAC for loudspeaker (4Ω/8Ω) and earphone (16Ω/32Ω).
Proceedings of the 36th European Solid-State Circuits Conference, 2010
2001
An eighth-order CMOS low-pass filter with 30-120 MHz tuning range and programmable boost.
IEEE J. Solid State Circuits, 2001
2000
A 450 Mbit/s parallel read/write channel with parity check and 16-state time variant Viterbi.
Proceedings of the IEEE 2000 Custom Integrated Circuits Conference, 2000
1999
Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999
1997
A 200-MSample/s trellis-coded PRML read/write channel with analog adaptive equalizer and digital servo.
IEEE J. Solid State Circuits, 1997