Giacinto Paolo Saggese

According to our database, Giacinto Paolo Saggese authored at least 21 papers between 2001 and 2022.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2022

Approximate Multipliers Using Static Segmentation: Error Analysis and Improvements.

Antonio Giuseppe Maria Strollo, Ettore Napoli, Davide De Caro, Nicola Petra, Giacinto Paolo Saggese, Gennaro Di Meo

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

A Novel Module-Sign Low-Power Implementation for the DLMS Adaptive Filter With Low Steady-State Error.

Gennaro Di Meo, Davide De Caro, Giacinto Paolo Saggese, Ettore Napoli, Nicola Petra, Antonio Giuseppe Maria Strollo

IEEE Trans. Circuits Syst. I Regul. Pap., 2022

2011

Automated Derivation of Application-Specific Error Detectors Using Dynamic Analysis.

Karthik Pattabiraman, Giacinto Paolo Saggese, Daniel Chen, Zbigniew Kalbarczyk, Ravishankar K. Iyer

IEEE Trans. Dependable Secur. Comput., 2011

2006

Dynamic Derivation of Application-Specific Error Detectors and their Implementation in Hardware.

Karthik Pattabiraman, Giacinto Paolo Saggese, Daniel Chen, Zbigniew Kalbarczyk, Ravishankar K. Iyer

Proceedings of the Sixth European Dependable Computing Conference, 2006

2005

An Experimental Study of Soft Errors in Microprocessors.

Giacinto Paolo Saggese, Nicholas J. Wang, Zbigniew Kalbarczyk, Sanjay J. Patel, Ravishankar K. Iyer

IEEE Micro, 2005

An Architectural Framework for Detecting Process Hangs/Crashes.

Nithin Nakka, Giacinto Paolo Saggese, Zbigniew Kalbarczyk, Ravishankar K. Iyer

Proceedings of the Dependable Computing, 2005

Microprocessor Sensitivity to Failures: Control vs Execution and Combinational vs Sequential Logic.

Giacinto Paolo Saggese, Anoop Vetteth, Zbigniew Kalbarczyk, Ravishankar K. Iyer

Proceedings of the 2005 International Conference on Dependable Systems and Networks (DSN 2005), 28 June, 2005

2004

Exploring the design-space for FPGA-based implementation of RSA.

Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese

Microprocess. Microsystems, 2004

A Web Services Based Architecture for Digital Time Stamping.

Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese, Giuseppe Cattaneo

J. Web Eng., 2004

A tamper resistant hardware accelerator for RSA cryptographic applications.

Giacinto Paolo Saggese, Luigi Romano, Nicola Mazzocca, Antonino Mazzeo

J. Syst. Archit., 2004

Hardware Support for High Performance, Intrusion- and Fault-Tolerant Systems.

Giacinto Paolo Saggese, Claudio Basile, Luigi Romano, Zbigniew Kalbarczyk, Ravishankar K. Iyer

Proceedings of the 23rd International Symposium on Reliable Distributed Systems (SRDS 2004), 2004

Carry-Save Montgomery Modular Exponentiation on Reconfigurable Hardware.

Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese

Proceedings of the 2004 Design, 2004

2003

Using programmable hardware to improve the dependability of cryptographic applications.

Giacinto Paolo Saggese

PhD thesis, 2003

Providing Digital Time Stamping Services to Mobile Devices.

Domenico Cotroneo, Cristiano di Flora, Antonino Mazzeo, Luigi Romano, Stefano Russo, Giacinto Paolo Saggese

Proceedings of the 9th IEEE International Workshop on Object-Oriented Real-Time Dependable Systems (WORDS Fall 2003), 2003

Using Web Services Technology for Inter-enterprise Integration of Digital Time Stamping.

Alessandro Cilardo, Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese, Giuseppe Cattaneo

Proceedings of the On The Move to Meaningful Internet Systems 2003: OTM 2003 Workshops, 2003

An FPGA-Based Performance Analysis of the Unrolling, Tiling, and Pipelining of the AES Algorithm.

Giacinto Paolo Saggese, Antonino Mazzeo, Nicola Mazzocca, Antonio G. M. Strollo

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

FPGA-Based Implementation of a Serial RSA Processor.

Antonino Mazzeo, Luigi Romano, Giacinto Paolo Saggese, Nicola Mazzocca

Proceedings of the 2003 Design, 2003

2002

Shuffled serial adder: an area-latency effective serial adder.

Giacinto Paolo Saggese, Antonio G. M. Strollo, Nicola Mazzocca, Davide De Caro

Proceedings of the 2002 9th IEEE International Conference on Electronics, 2002

A Technique for FPGA Synthesis Driven by Automatic Source Code Analysis and Transformations.

Beniamino Di Martino, Nicola Mazzocca, Giacinto Paolo Saggese, Antonio G. M. Strollo

Proceedings of the Field-Programmable Logic and Applications, 2002

2001

A reconfigurable 2D convolver for real-time SAR imaging.

Antonio G. M. Strollo, Ettore Napoli, Davide De Caro, Giacinto Paolo Saggese

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001

Test pattern generator for hybrid testing of combinational circuits.

Davide De Caro, Nicola Mazzocca, Ettore Napoli, Giacinto Paolo Saggese, Antonio G. M. Strollo

Proceedings of the 2001 8th IEEE International Conference on Electronics, 2001