Gi-Ho Park

IEEE Trans. Parallel Distributed Syst., 2017

2016

Demand-Aware NVM Capacity Management Policy for Hybrid Cache Architecture.

[BibT_eX]

[DOI]

Ju Hee Choi

Comput. J., 2016

2015

Data Classification Management with its Interfacing Structure for Hybrid SLC/MLC PRAM Main Memory.

[BibT_eX]

[DOI]

Comput. J., 2015

2014

Adaptive replacement policy for hybrid cache architecture.

[BibT_eX]

[DOI]

Ju Hee Choi

IEICE Electron. Express, 2014

2012

Performance and energy-efficiency analysis of hybrid cache memory based on SRAM-MRAM.

[BibT_eX]

[DOI]

Byung-Min Lee

Proceedings of the International SoC Design Conference, 2012

2010

Design and implementation of Performance Analysis Unit (PAU) for AXI-based multi-core System on Chip (SOC).

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2010

An instruction-systolic programmable shader architecture for multi-threaded 3D graphics processing.

[BibT_eX]

[DOI]

J. Parallel Distributed Comput., 2010

Fully digital clock frequency doubler.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2010

2009

A Way Enabling Mechanism Based on the Branch Prediction Information for Low Power Instruction Cache.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2009

Low-Power Embedded Processor Design Using Branch Direction.

[BibT_eX]

[DOI]

IEICE Trans. Fundam. Electron. Commun. Comput. Sci., 2009

Sub-grouped superblock management for high-performance flash storages.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2009

An integrated mapping table for hybrid FTL with fault-tolerant address cache.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2009

2008

Power and Skew Aware Point Diffusion Clock Network.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2008

2007

Cooperative Cache System: A Low Power Cache System for Embedded Processors.

[BibT_eX]

[DOI]

IEICE Trans. Electron., 2007

Performance monitor unit design for an AXI-based multi-core SoC platform.

[BibT_eX]

[DOI]

Proceedings of the 2007 ACM Symposium on Applied Computing (SAC), 2007

An efficient scheme for parallelizing fast search algorithm on SIMD architecture in H.264/AVC.

[BibT_eX]

Proceedings of the ISCA 20th International Conference on Parallel and Distributed Computing Systems, 2007

2006

A deterministic way-prediction scheme using power-aware replacement policy.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2006

Sim-ARM1136: A case study on the accuracy of the cycle-accurate simulator.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2006

Practice and Experience of an Embedded Processor Core Modeling.

[BibT_eX]

[DOI]

Proceedings of the High Performance Computing and Communications, 2006

Low-Power Data Cache Architecture by Address Range Reconfiguration for Multimedia Applications.

[BibT_eX]

[DOI]

Hoon-Mo Yang

Proceedings of the Advances in Computer Systems Architecture, 11th Asia-Pacific Conference, 2006

2005

p-Refinement Techniques for Vector Finite Elements in Electromagnetics.

[BibT_eX]

[DOI]

PhD thesis, 2005

A new NAND-type flash memory package with smart buffer system for spatial and temporal localities.

[BibT_eX]

[DOI]

J. Syst. Archit., 2005

2004

Dynamic and selective low power data TLB system.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2004

A Low-Power Branch Predictor for Embedded Processors.

[BibT_eX]

[DOI]

Sung Woo Chung

Sung-Bae Park

IEICE Trans. Inf. Syst., 2004

A Low-Power Tournament Branch Predictor.

[BibT_eX]

[DOI]

Sung Woo Chung

Sung-Bae Park

IEICE Trans. Inf. Syst., 2004

Power-Aware Deterministic Block Allocation for Low-Power Way-Selective Cache Structure.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE International Conference on Computer Design: VLSI in Computers & Processors (ICCD 2004), 2004

2003

An Adaptive Multi-Module Cache with Hardware Prefetching Mechanism for Multimedia Applications.

[BibT_eX]

[DOI]

Proceedings of the 11th Euromicro Workshop on Parallel, 2003

A selective filter-bank TLB system.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Low Power Electronics and Design, 2003

Appliaction-Specific Data Cache Systems.

[BibT_eX]

Proceedings of the ISCA 18th International Conference Computers and Their Applications, 2003

2002

An Advanced Filtering TLB for Low Power Consumption.

[BibT_eX]

[DOI]

Proceedings of the 14th Symposium on Computer Architecture and High Performance Computing (SBAC-PAD 2002), 2002

2000

A Dual Data Cache System to Reflect the Principle of Locality Effectively.

[BibT_eX]

Proceedings of the International Conference on Parallel and Distributed Processing Techniques and Applications, 2000

A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure.

[BibT_eX]

[DOI]

Proceedings of the Languages, 2000

1998

Methods to improve performance of instruction prefetching through balanced improvement of two primary performance factors.

[BibT_eX]

[DOI]

J. Syst. Archit., 1998

1996

A compiler optimization to reduce execution time of loop nest.

[BibT_eX]

[DOI]

Oh-Young Kwon