Ghavam G. Shahidi

According to our database, Ghavam G. Shahidi authored at least 16 papers between 1989 and 2020.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2020

EM-Side-Channel Resistant Symmetric-Key Authentication Mechanism for Small Devices.

Rick Boivie, Charanjit S. Jutla, Daniel Friedman, Ghavam G. Shahidi

IACR Cryptol. ePrint Arch., 2020

Chip Power-Frequency Scaling in 10/7nm Node.

Phil Oldiges, Reinaldo A. Vega, Henry K. Utomo, Nick A. Lanzillo, Thomas Wassick, Juntao Li, Junli Wang, Ghavam G. Shahidi

IEEE Access, 2020

2019

Chip Power Scaling in Recent CMOS Technology Nodes.

Ghavam G. Shahidi

IEEE Access, 2019

Slow-Down in Power Scaling and the End of Moore's Law?

Ghavam G. Shahidi

Proceedings of the International Symposium on VLSI Design, Automation and Test, 2019

2013

From 2D-planar to 3D-non-planar device architecture: A scalable path forward?

Ghavam G. Shahidi

Proceedings of the IEEE 2013 Custom Integrated Circuits Conference, 2013

2010

Fully depleted extremely thin SOI for mainstream 20nm low-power technology and beyond.

Ali Khaki-Firooz, Kangguo Cheng, Basanth Jagannathan, Pranita Kulkarni, Jeffrey W. Sleight, Davood Shahrjerdi, Josephine B. Chang, Sungjae Lee, Junjun Li, Huiming Bu, Robert Gauthier, Bruce Doris, Ghavam G. Shahidi

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

2007

Evolution of CMOS Technology at 32 nm and Beyond.

Ghavam G. Shahidi

Proceedings of the IEEE 2007 Custom Integrated Circuits Conference, 2007

2006

Optimizing CMOS technology for maximum performance.

David J. Frank, Wilfried Haensch, Ghavam G. Shahidi, Omer H. Dokumaci

IBM J. Res. Dev., 2006

2002

SOI technology for the GHz era.

Ghavam G. Shahidi

IBM J. Res. Dev., 2002

1999

Device and circuit design issues in SOI technology.

Ghavam G. Shahidi, Atul Ajmera, Fariborz Assaderaghi, Ronald J. Bolam, Harold Hovel, Effendi Leobandung, Werner Rausch, Devendra Sadana, Dominic Schepis, Lawrence F. Wagner, Larry Wissel, Kun Wu, Bijan Davai

Proceedings of the IEEE 1999 Custom Integrated Circuits Conference, 1999

1997

SRAM bitline circuits on PD SOI: advantages and concerns.

Jente B. Kuang, Somnuk Ratanaphanyarat, Mary Jo Saccamango, Louis L.-C. Hsu, Roy C. Flaker, Lawrence F. Wagner, Shao-Fu Sanford Chu, Ghavam G. Shahidi

IEEE J. Solid State Circuits, 1997

1996

250-600 Mhz 12b digital filters in 0.8-0.25um Bulk and SOI CMOS technologies.

Lars E. Thon, Ghavam G. Shahidi, Werner Rausch, Gerald P. Coleman, Denny D. Tang, Dominic Schepis, Ronald Schulz, Fariborz Assadaraghi

Proceedings of the 1996 International Symposium on Low Power Electronics and Design, 1996

1995

CMOS scaling for high performance and low power-the next ten years.

Bijan Davari, Robert H. Dennard, Ghavam G. Shahidi

Proc. IEEE, 1995

CMOS scaling in the 0.1-µm, 1.X-volt regime for high-performance applications.

Ghavam G. Shahidi, James D. Warnock, James Comfort, Stephen E. Fischer, Patricia A. McFarland, Alexandre Acovic, Terry I. Chappell, Barbara A. Chappell, Tak H. Ning, Carl J. Anderson, Robert H. Dennard, Jack Y.-C. Sun, Michael R. Polcari, Bijan Davari

IBM J. Res. Dev., 1995

A half-micron CMOS logic generation.

Charles W. Koburger III, William F. Clark, James W. Adkisson, Eric Adler, Paul E. Bakeman, Albert S. Bergendahl, Alan B. Botula, W. Chang, Bijan Davari, John H. Givens, Howard H. Hansen, Steven J. Holmes, David V. Horak, Chung Hon Lam, Jerome B. Lasky, Stephen E. Luce, Randy W. Mann, Glen L. Miles, James S. Nakos, Edward J. Nowak, Ghavam G. Shahidi, Yuan Taur, Francis R. White, Matthew R. Wordeman

IBM J. Res. Dev., 1995

1989

Non-stationary transport effects in deep sub-micron channel Si mosfets.

Ghavam G. Shahidi

PhD thesis, 1989