Ghassem Jaberipur
Orcid: 0000-0001-8458-7627
According to our database1,
Ghassem Jaberipur
authored at least 60 papers
between 2005 and 2025.
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Bibliography
2025
Poster: Integration of Wearable and Affective Computing via Abstraction and Decision Fusion Architecture.
Proceedings of the 25th IEEE International Symposium on a World of Wireless, 2025
2024
Low-cost constant time signed digit selection for most significant bit first multiplication.
Microprocess. Microsystems, 2024
CoRR, 2024
IEEE Access, 2024
Proceedings of the 31st IEEE Symposium on Computer Arithmetic, 2024
2023
A Parallel Prefix Modulo-(2<sup>q</sup> + 2<sup>q-1</sup> + 1) Adder via Diminished-1 Representation of Residues.
IEEE Trans. Circuits Syst. II Express Briefs, August, 2023
Modulo-(2<sup>q</sup> - 3) Multiplication with Fully Modular Partial Product Generation and Reduction.
Proceedings of the 30th IEEE Symposium on Computer Arithmetic, 2023
2022
Impact of Radix-10 Redundant Digit Set [-6, 9] on Basic Decimal Arithmetic Operations.
IEEE Trans. Very Large Scale Integr. Syst., 2022
Up to $8k$8k-bit Modular Montgomery Multiplication in Residue Number Systems With Fast 16-bit Residue Channels.
IEEE Trans. Computers, 2022
Efficient variable-coefficient RNS-FIR filters with no restriction on the moduli set.
Signal Image Video Process., 2022
2020
Balanced $(3+2\log n)\Delta G$ Adders for Moduli Set $\{{2}^{n+1}, 2^{n}+2^{n-1}-1, 2^{n+1}-1\}$.
IEEE Trans. Circuits Syst. I Fundam. Theory Appl., 2020
Design of an efficient fully nonvolatile and radiation-hardened majority-based magnetic full adder using FinFET/MTJ.
Microelectron. J., 2020
Fast division in the residue number system {2<i><sup>n</sup></i> + 1, 2<i><sup>n</sup></i>, 2<i><sup>n</sup></i>-1} based on shortcut mixed radix conversion.
Comput. Electr. Eng., 2020
Comput. Electr. Eng., 2020
2019
Impact of diminished-1 encoding on residue number systems arithmetic units and converters.
Comput. Electr. Eng., 2019
Proceedings of the 26th IEEE Symposium on Computer Arithmetic, 2019
2018
Adapting Computer Arithmetic Structures to Sustainable Supercomputing in Low-Power, Majority-Logic Nanotechnologies.
IEEE Trans. Sustain. Comput., 2018
ACM Trans. Embed. Comput. Syst., 2018
IEEE Trans. Circuits Syst. I Regul. Pap., 2018
IEEE Trans. Circuits Syst. II Express Briefs, 2018
2017
IEEE Trans. Very Large Scale Integr. Syst., 2017
Energy-Efficient VLSI Realization of Binary64 Division With Redundant Number Systems.
IEEE Trans. Very Large Scale Integr. Syst., 2017
Microprocess. Microsystems, 2017
(5 + 2⌈log n⌉)ΔG diminished-1 modulo-(2<sup>n</sup>+1) unified adder/subtractor with full zero handling.
Comput. Electr. Eng., 2017
2016
IEEE Trans. Very Large Scale Integr. Syst., 2016
Fast low energy RNS comparators for 4-moduli sets {2<sup>n</sup>±1, 2<sup>n</sup>, m} with m∈{2<sup>n+1</sup>±1, 2<sup>n-1</sup>-1}.
Integr., 2016
Circuits Syst. Signal Process., 2016
Comput. Electr. Eng., 2016
Conditional speculative mixed decimal/binary adders via binary-coded-chiliad encoding.
Comput. Electr. Eng., 2016
A Formulation of Fast Carry Chains Suitable for Efficient Implementation with Majority Elements.
Proceedings of the 23nd IEEE Symposium on Computer Arithmetic, 2016
2015
(4+2 log n)ΔG Parallel Prefix Modulo-(2<sup>n</sup>-3) Adder via Double Representation of Residues in [0, 2].
IEEE Trans. Circuits Syst. II Express Briefs, 2015
Comment on "High Speed Parallel Decimal Multiplication With Redundant Internal Encodings".
IEEE Trans. Computers, 2015
A New Residue Number System with 5-Moduli Set: {2<sup>2<i>q</i></sup>, 2<sup><i>q</i></sup>±3, 2<sup><i>q</i></sup>±1}.
Comput. J., 2015
Modulo-(2<sup>n</sup> - 2<sup>q</sup> - 1) Parallel Prefix Addition via Excess-Modulo Encoding of Residues.
Proceedings of the 22nd IEEE Symposium on Computer Arithmetic, 2015
2014
Low area/power decimal addition with carry-select correction and carry-select sum-digits.
Integr., 2014
IET Comput. Digit. Tech., 2014
Circuits Syst. Signal Process., 2014
Proceedings of the International Conference on Systems, Signals and Image Processing, 2014
2012
Efficient realisation of arithmetic algorithms with weighted collection of posibits and negabits.
IET Comput. Digit. Tech., 2012
Comput. Electr. Eng., 2012
2011
Comput. J., 2011
Proceedings of the 20th IEEE Symposium on Computer Arithmetic, 2011
Proceedings of the Conference Record of the Forty Fifth Asilomar Conference on Signals, 2011
2010
IEEE Trans. Computers, 2010
Integr., 2010
2009
Microelectron. J., 2009
Unified Approach to the Design of Modulo-(2<sup>n</sup> +/- 1) Adders Based on Signed-LSB Representation of Residues.
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009
Proceedings of the 19th IEEE Symposium on Computer Arithmetic, 2009
2008
Integr., 2008
Proceedings of the Advances in Computer Science and Engineering, 2008
2007
Stored-transfer representations with weighted digit-set encodings for ultrahigh-speed arithmetic.
IET Circuits Devices Syst., 2007
2006
An Efficient Universal Addition Scheme for All Hybrid-Redundant Representations with Weighted Bit-Set Encoding.
J. VLSI Signal Process., 2006
2005
Weighted two-valued digit-set encodings: unifying efficient hardware representation schemes for redundant number systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2005