Geunho Cho

According to our database1, Geunho Cho authored at least 5 papers between 2010 and 2016.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
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Links

On csauthors.net:

Bibliography

2016
Design and process variation analysis of CNTFET-based ternary memory cells.
Integr., 2016

2013
On the Delay of a CNTFET with Undeposited CNTs by Gate Width Adjustment.
J. Electron. Test., 2013

A novel and improved design of a ternary CNTFET-based cell.
Proceedings of the Great Lakes Symposium on VLSI 2013 (part of ECRC), 2013

2011
On the Delay Analysis of Defective CNTFETs with Undeposited CNTs.
Proceedings of the 2011 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2011

2010
Modelling a CNTFET with Undeposited CNT Defects.
Proceedings of the 25th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems, 2010


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