Geun Rae Cho
According to our database1,
Geun Rae Cho
authored at least 10 papers
between 2001 and 2014.
Collaborative distances:
Collaborative distances:
Timeline
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Book In proceedings Article PhD thesis Dataset OtherLinks
On csauthors.net:
Bibliography
2014
Framework for simulation of the Verilog/SPICE mixed model: Interoperation of Verilog and SPICE simulators using HLA/RTI for model reusability.
Proceedings of the 22nd International Conference on Very Large Scale Integration, 2014
2013
IEICE Electron. Express, 2013
2004
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2004
2003
On Single/Dual-Rail Mixed PTL/Static Circuits in Floating-Body SOI and Bulk CMOS: A Comparative Assessment.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003
Proceedings of the 4th International Symposium on Quality of Electronic Design (ISQED 2003), 2003
2002
Applications of Evolution Algorithms to the synthesis of single/Dual-rail mixed PTL/Static Logic for low-Power Applications.
Proceedings of the Recent Advances in Simulated Evolution and Learning [extended and revised papers selected from the 4th Asia-Pacific Conference on Simulated Evolution and Learning, 2002
On the Impact of Fanout Optimization and Redundant Buffer Removal for Mixed PTL Synthesis.
Proceedings of the 11th IEEE/ACM International Workshop on Logic & Synthesis, 2002
Mixed PTL/Static Logic Synthesis Using Genetic Algorithms for Low-Power Applications.
Proceedings of the 3rd International Symposium on Quality of Electronic Design, 2002
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002
2001