Gerry Taylor

According to our database, Gerry Taylor authored at least 10 papers between 2010 and 2024.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2024

A -90-dBFS-IM₃, -164-dBFS/Hz-NSD, 700-MHz-Bandwidth Continuous-Time Pipelined ADC With Digital Cancellation of DAC Errors.

Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Prawal Shrestha, Zhao Li, Sevil Zeynep Lulec, Konstantinos Vasilakopoulos, Raviteja Theertham, Donald Paterson, Qingnan Yu, Aseer Chowdhury

IEEE J. Solid State Circuits, December, 2024

22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors.

Sharvil Patil, Asha Ganesan, Hajime Shibata, Victor Kozlov, Gerry Taylor, Qingnan Yu, Zhao Li, Zeynep Lulec, Konstantinos Vasilakopoulos, Prawal Shrestha, Donald Paterson, Raviteja Theertham, Aseer Chowdhury

Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2020

16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter.

Hajime Shibata, Gerry Taylor, Bob Schell, Victor Kozlov, Sharvil Patil, Donald Paterson, Asha Ganesan, Yunzhi Dong, Wenhua Yang, Yue Yin, Zhao Li, Prawal Shrestha, Athreya Gopal, Aathreya S. Bhat, Shanthi Pavan

Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2016

A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither.

Ahmed M. A. Ali, Hüseyin Dinc, Paritosh Bhoraskar, Scott Puckett, Andy Morgan, Ning Zhu, Qicheng Yu, Christopher Dillon, Bryce Gray, Jonathan Lanford, Matthew McShea, Ushma Mehta, Scott Bardsley, Peter R. Derounian, Ryan Bunch, Ralph Moore, Gerry Taylor

Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2013

A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB.

Gerry Taylor, Ian Galton

IEEE J. Solid State Circuits, 2013

2012

A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160dB.

Gerry Taylor, Ian Galton

Proceedings of the Symposium on VLSI Circuits, 2012

2011

Correction to "A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC" [Nov 10 2250-2261].

Gerry Taylor, Ian Galton

IEEE J. Solid State Circuits, 2011

2010

A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC.

Gerry Taylor, Ian Galton

IEEE J. Solid State Circuits, 2010

A mostly digital variable-rate continuous-time ADC ΔΣ modulator.

Gerry Taylor, Ian Galton

Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 65nm CMOS low-power small-size multistandard, multiband mobile broadcasting receiver SoC.

Minsu Jeong, Bonkee Kim, Youngho Cho, Yanggyun Kim, Seyeob Kim, Heeyong Yoo, Junghwan Lee, Jae Kyung Lee, Kyung Soo Jung, Jeiyoung Lee, Junghun Lee, Huikwan Yang, Gerry Taylor, Boeun Kim

Proceedings of the IEEE International Solid-State Circuits Conference, 2010