Gerry Taylor

According to our database1, Gerry Taylor authored at least 9 papers between 2010 and 2024.

Collaborative distances:
  • Dijkstra number2 of five.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

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Bibliography

2024
22.2 A 700MHZ-BW -164dBFS/Hz-Small-Signal-NSD 703mW Continuous-Time Pipelined ADC with On-Chip Digital Reconstruction Achieving 3 using Digital Cancellation of DAC Errors.
Proceedings of the IEEE International Solid-State Circuits Conference, 2024

2020
16.6 An 800MHz-BW VCO-Based Continuous-Time Pipelined ADC with Inherent Anti-Aliasing and On-Chip Digital Reconstruction Filter.
Proceedings of the 2020 IEEE International Solid- State Circuits Conference, 2020

2016
A 14-bit 2.5GS/s and 5GS/s RF sampling ADC with background calibration and dither.
Proceedings of the 2016 IEEE Symposium on VLSI Circuits, 2016

2013
A Reconfigurable Mostly-Digital Delta-Sigma ADC With a Worst-Case FOM of 160 dB.
IEEE J. Solid State Circuits, 2013

2012
A reconfigurable mostly-digital ΔΣ ADC with a worst-case FOM of 160dB.
Proceedings of the Symposium on VLSI Circuits, 2012

2011
Correction to "A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC" [Nov 10 2250-2261].
IEEE J. Solid State Circuits, 2011

2010
A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC.
IEEE J. Solid State Circuits, 2010

A mostly digital variable-rate continuous-time ADC ΔΣ modulator.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010

A 65nm CMOS low-power small-size multistandard, multiband mobile broadcasting receiver SoC.
Proceedings of the IEEE International Solid-State Circuits Conference, 2010


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