Gerhard Knoblinger

According to our database1, Gerhard Knoblinger authored at least 21 papers between 2001 and 2021.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2021
A 12-b 16-GS/s RF-Sampling Capacitive DAC for Multi-Band Soft Radio Base-Station Applications With On-Chip Transmission-Line Matching Network in 16-nm FinFET.
IEEE J. Solid State Circuits, 2021

2018
A 28nm Low-Voltage Digital Power-Amplifier for QAM-256 WIFI Applications in 0.5mm<sup>2</sup> Area w/ 2D Digital-Pre-Distortion and Package Combiner.
Proceedings of the 25th IEEE International Conference on Electronics, Circuits and Systems, 2018

2017
13.9 A 1.1V 28.6dBm fully integrated digital power amplifier for mobile and wireless applications in 28nm CMOS technology with 35% PAE.
Proceedings of the 2017 IEEE International Solid-State Circuits Conference, 2017

2015
Analysis and design of a 1.1dB-IL third-order Matching Network for Switched-Capacitor PAs.
Proceedings of the Nordic Circuits and Systems Conference, 2015

Switched state-space model for a switched-capacitor power amplifier.
Proceedings of the 2015 IEEE International Symposium on Circuits and Systems, 2015

2011
LC-VCO in the 3.3- to 4-GHz Band Implemented in 32-nm Low-Power CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2011

2009
Design of Ultra-Wideband Low-Noise Amplifiers in 45-nm CMOS Technology: Comparison Between Planar Bulk and SOI FinFET Devices.
IEEE Trans. Circuits Syst. I Regul. Pap., 2009

Design of Low-Voltage Bandgap Reference Circuits in Multi-Gate CMOS Technologies.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2009), 2009

Assessment of the impact of technology scaling on the performance of LC-VCOs.
Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008
Design of UWB LNA in 45nm CMOS technology: Planar bulk vs. FinFET.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

2007
A merged MuGFET and planar SOI process.
Proceedings of the 2007 IEEE International SOC Conference, 2007

SUB-45nm Technology and Design Challenges.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Multi-Gate MOSFET Design.
Proceedings of the 8th International Symposium on Quality of Electronic Design (ISQED 2007), 2007

Transient Variations in Emerging SOI Technologies: Modeling and Impact on Analog/Mixed-Signal Circuits.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2007), 2007

Advances in Multi-Gate MOSFET Circuit Design.
Proceedings of the 14th IEEE International Conference on Electronics, 2007

Analog design challenges and trade-offs using emerging materials and devices.
Proceedings of the 33rd European Solid-State Circuits Conference, 2007

2006
Circuit design issues in multi-gate FET CMOS technologies.
Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

Dielectric absorption of low-k materials: extraction, modelling and influence on SAR ADCs.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

2002
Modeling the gate-related high-frequency and noise characteristics of deep-submicron MOSFETs.
Proceedings of the IEEE 2002 Custom Integrated Circuits Conference, 2002

2001
A new model for thermal channel noise of deep-submicron MOSFETs and its application in RF-CMOS design.
IEEE J. Solid State Circuits, 2001

When do we need non-quasistatic CMOS RF-models?
Proceedings of the IEEE 2001 Custom Integrated Circuits Conference, 2001


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