Gerd Spalink

According to our database, Gerd Spalink authored at least 4 papers between 2022 and 2023.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2023

A Digital PLL-Based Phase Modulator With Non-Uniform Clock Compensation and Non-linearity Predistortion.

Zhong Gao, Martin Fritz, Gerd Spalink, Robert Bogdan Staszewski, Masoud Babaie

IEEE J. Solid State Circuits, September, 2023

A Low-Spur Fractional-N PLL Based on a Time-Mode Arithmetic Unit.

Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Morteza S. Alavi, Robert Bogdan Staszewski, Masoud Babaie

IEEE J. Solid State Circuits, 2023

2022

A DPLL-Based Phase Modulator Achieving -46dB EVM with A Fast Two-Step DCO Nonlinearity Calibration and Non-Uniform Clock Compensation.

Zhong Gao, Martin Fritz, Jingchu He, Gerd Spalink, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie

Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022

A 2.6-to-4.1GHz Fractional-N Digital PLL Based on a Time-Mode Arithmetic Unit Achieving -249.4dB FoM and -59dBc Fractional Spurs.

Zhong Gao, Jingchu He, Martin Fritz, Jiang Gong, Yiyu Shen, Zhirui Zong, Peng Chen, Gerd Spalink, Ben Eitel, Ken Yamamoto, Robert Bogdan Staszewski, Morteza S. Alavi, Masoud Babaie

Proceedings of the IEEE International Solid-State Circuits Conference, 2022