Geraldine Shirley

According to our database, Geraldine Shirley authored at least 9 papers between 2019 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2024

AutoDetect: Novel Autoencoding Architecture for Counterfeit IC Detection.

Chaitanya Bhure, Geraldine Shirley Nicholas, Shajib Ghosh, Navid Asadi, Fareena Saqib

J. Hardw. Syst. Secur., June, 2024

2023

Secure Instruction and Data-Level Information Flow Tracking Model for RISC-V.

Geraldine Shirley Nicholas, Dhruvakumar Vikas Aklekar, Bhavin Thakar, Fareena Saqib

Cryptogr., September, 2023

2022

Dynamic Key Updates for LUT Locked Design.

Jakub Slowik, Gregory Williams, Rummah Albashir, Anthony Samagio, Geraldine Shirley Nicholas, Fareena Saqib

Proceedings of the IEEE International Symposium on Hardware Oriented Security and Trust, 2022

2021

A Secure Boot Framework with Multi-security Features and Logic-Locking Applications for Reconfigurable Logic.

Geraldine Shirley Nicholas, Ali Shuja Siddiqui, Sam Reji Joseph, Gregory Williams, Fareena Saqib

J. Hardw. Syst. Secur., 2021

A Lightweight Delay-based Authentication Scheme for DMA Attack Mitigation.

Yutian Gui, Ali Shuja Siddiqui, Geraldine Shirley Nicholas, Marcus Hughes, Fareena Saqib

Proceedings of the 22nd International Symposium on Quality Electronic Design, 2021

Hardware Secure Execution and Simulation Model Correlation using IFT on RISC-V.

Geraldine Shirley Nicholas, Bhavin Thakar, Fareena Saqib

Proceedings of the GLSVLSI '21: Great Lakes Symposium on VLSI 2021, 2021

2020

A Survey and Analysis on SoC Platform Security in ARM, Intel and RISC-V Architecture.

Geraldine Shirley Nicholas, Yutian Gui, Fareena Saqib

Proceedings of the 63rd IEEE International Midwest Symposium on Circuits and Systems, 2020

2019

Multilayer Camouflaged Secure Boot for SoCs.

Ali Shuja Siddiqui, Geraldine Shirley, Sam Reji Joseph, Yutian Gui, Jim Plusquellic, Marten van Dijk, Fareena Saqib

Proceedings of the 20th International Workshop on Microprocessor/SoC Test, 2019

Secure Design Flow of FPGA Based RISC-V Implementation.

Ali Shuja Siddiqui, Geraldine Shirley, Shreya Bendre, Girija Bhagwat, Jim Plusquellic, Fareena Saqib

Proceedings of the 4th IEEE International Verification and Security Workshop, 2019