Georgios Vavouliotis

Orcid: 0000-0002-5416-6634

According to our database¹, Georgios Vavouliotis authored at least 8 papers between 2021 and 2025.

Collaborative distances:

Dijkstra number² of four.
Erdős number³ of four.

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Bibliography

2025

Instruction-Aware Cooperative TLB and Cache Replacement Policies.

[BibT_eX]

[DOI]

Proceedings of the 30th ACM International Conference on Architectural Support for Programming Languages and Operating Systems, 2025

2024

Advanced hardware prefetching in virtual memory systems

[BibT_eX]

[DOI]

Georgios Vavouliotis

PhD thesis, 2024

Practically Tackling Memory Bottlenecks of Graph-Processing Workloads.

[BibT_eX]

[DOI]

Alexandre Valentin Jamet

Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2024

A Two Level Neural Approach Combining Off-Chip Prediction with Adaptive Prefetch Filtering.

[BibT_eX]

[DOI]

Alexandre Valentin Jamet

Proceedings of the IEEE International Symposium on High-Performance Computer Architecture, 2024

2023

Concurrent GCs and Modern Java Workloads: A Cache Perspective.

[BibT_eX]

[DOI]

Maria Carpen-Amarie

Georgios Vavouliotis

Konstantinos Tovletoglou

Boris Grot

René Müller

Proceedings of the 2023 ACM SIGPLAN International Symposium on Memory Management, 2023

2022

Page Size Aware Cache Prefetching.

[BibT_eX]

[DOI]

Proceedings of the 55th IEEE/ACM International Symposium on Microarchitecture, 2022

2021

Morrigan: A Composite Instruction TLB Prefetcher.

[BibT_eX]

[DOI]

Proceedings of the MICRO '21: 54th Annual IEEE/ACM International Symposium on Microarchitecture, 2021

Exploiting Page Table Locality for Agile TLB Prefetching.

[BibT_eX]

[DOI]

Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

Georgios Vavouliotis

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