Georgios Papandroulidakis

Orcid: 0000-0002-9203-2557

According to our database1, Georgios Papandroulidakis authored at least 8 papers between 2014 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

Legend:

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PhD thesis 
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Links

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Bibliography

2024
A 9T4R RRAM-Based ACAM for Analogue Template Matching at the Edge.
CoRR, 2024

2023
A 1T1R+2T Analog Content-Addressable Memory Pixel for Online Template Matching.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023

2019
Practical Implementation of Memristor-Based Threshold Logic Gates.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

A Digital In-Analogue Out Logic Gate Based on Metal-Oxide Memristor Devices.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2019

2018
Processing big-data with Memristive Technologies: Splitting the Hyperplane Efficiently.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

Metal Oxide-enabled Reconfigurable Memristive Threshold Logic Gates.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2018

2016
2T1M-Based Double Memristive Crossbar Architecture for In-Memory Computing.
Int. J. Unconv. Comput., 2016

2014
Boolean Logic Operations and Computing Circuits Based on Memristors.
IEEE Trans. Circuits Syst. II Express Briefs, 2014


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