Georgios K. Konstadinidis

Affiliations:
  • Oracle, Santa Clara, CA, USA


According to our database1, Georgios K. Konstadinidis authored at least 15 papers between 1992 and 2016.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of two.

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
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Links

On csauthors.net:

Bibliography

2016
SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor.
IEEE J. Solid State Circuits, 2016

2015
M7: Oracle's Next-Generation Sparc Processor.
IEEE Micro, 2015


4.3 Fine-grained adaptive power management of the SPARC M7 processor.
Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014
A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm.
IEEE J. Solid State Circuits, 2014

2013
The Next Generation 64b SPARC Core in a T4 SoC Processor.
IEEE J. Solid State Circuits, 2013


2012
The next-generation 64b SPARC core in a T4 SoC processor.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2009
Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor.
IEEE J. Solid State Circuits, 2009

2008
Implementation of a Third-Generation 16-Core 32-Thread Chip-Multithreading SPARCs® Processor.
Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2005
Introduction to the Special Issue on the ISSCC2004.
IEEE J. Solid State Circuits, 2005

2002
Implementation of a third-generation 1.1-GHz 64-bit microprocessor.
IEEE J. Solid State Circuits, 2002

Timing Window Applications in UltraSPARC-IIIi? Microprocessor Design.
Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

1994
Concurrent multipath power delay optimization for high speed digital VLSI systems.
PhD thesis, 1994

1992
Optimization of buffer stages in bipolar VLSI systems.
IEEE J. Solid State Circuits, July, 1992


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