Georgios K. Konstadinidis

According to our database, Georgios K. Konstadinidis authored at least 15 papers between 1992 and 2016.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of two.

2016

SPARC M7: A 20 nm 32-Core 64 MB L3 Cache Processor.

Georgios K. Konstadinidis, Hongping Penny Li, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister, Jeffrey Brooks, Ha Pham, Sebastian Turullols, Yifan YangGong, Robert T. Golla, Alan P. Smith, Ali Vahidsafa

IEEE J. Solid State Circuits, 2016

2015

M7: Oracle's Next-Generation Sparc Processor.

Kathirgamar Aingaran, Sumti Jairath, Georgios K. Konstadinidis, Serena Leung, Paul Loewenstein, Curtis McAllister, Stephen Phillips, Zoran Radovic, Ram Sivaramakrishnan, David Smentek, Thomas Wicki

IEEE Micro, 2015

4.2 A 20nm 32-Core 64MB L3 cache SPARC M7 processor.

Penny Li, Jinuk Luke Shin, Georgios K. Konstadinidis, Francis Schumacher, Venkatram Krishnaswamy, Hoyeol Cho, Sudesna Dash, Robert P. Masleid, Chaoyang Zheng, Yuanjung David Lin, Paul Loewenstein, Heechoul Park, Vijay Srinivasan, Dawei Huang, Changku Hwang, Wenjay Hsu, Curtis McAllister

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

4.3 Fine-grained adaptive power management of the SPARC M7 processor.

Venkatram Krishnaswamy, Jeffrey Brooks, Georgios K. Konstadinidis, Curtis McAllister, Ha Pham, Sebastian Turullols, Jinuk Luke Shin, Yifan YangGong, Haowei Zhang

Proceedings of the 2015 IEEE International Solid-State Circuits Conference, 2015

2014

A 3.6 GHz 16-Core SPARC SoC Processor in 28 nm.

Jason Hart, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Venkatram Krishnaswamy, Lance Kwong, Robert P. Masleid, Rakesh Mehta, Umesh Nawathe, Aparna Ramachandran, Harikaran Sathianathan, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen

IEEE J. Solid State Circuits, 2014

2013

The Next Generation 64b SPARC Core in a T4 SoC Processor.

Jinuk Luke Shin, Robert T. Golla, Hongping Penny Li, Sudesna Dash, Youngmoon Choi, Alan P. Smith, Harikaran Sathianathan, Mayur Joshi, Heechoul Park, Mohamed Elgebaly, Sebastian Turullols, Song Kim, Robert P. Masleid, Georgios K. Konstadinidis, Mary Jo Doherty, Greg Grohoski, Curtis McAllister

IEEE J. Solid State Circuits, 2013

3.6GHz 16-core SPARC SoC processor in 28nm.

Jason Hart, Steve Butler, Hoyeol Cho, Yuefei Ge, Gregory Gruber, Dawei Huang, Changku Hwang, Daisy Jian, Timothy Johnson, Georgios K. Konstadinidis, Lance Kwong, Robert P. Masleid, Umesh Nawathe, Aparna Ramachandran, Yongning Sheng, Jinuk Luke Shin, Sebastian Turullols, Zuxu Qin, King C. Yen

Proceedings of the 2013 IEEE International Solid-State Circuits Conference, 2013

2012

The next-generation 64b SPARC core in a T4 SoC processor.

Jinuk Luke Shin, Heechoul Park, Hongping Penny Li, Alan P. Smith, Youngmoon Choi, Harikaran Sathianathan, Sudesna Dash, Sebastian Turullols, Song Kim, Robert P. Masleid, Georgios K. Konstadinidis, Robert T. Golla, Mary Jo Doherty, Greg Grohoski, Curtis McAllister

Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

2009

Architecture and Physical Implementation of a Third Generation 65 nm, 16 Core, 32 Thread Chip-Multithreading SPARC Processor.

Georgios K. Konstadinidis, Marc Tremblay, Shailender Chaudhry, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar

IEEE J. Solid State Circuits, 2009

2008

Implementation of a Third-Generation 16-Core 32-Thread Chip-Multithreading SPARCs® Processor.

Georgios K. Konstadinidis, Mamun Rashid, Peter F. Lai, Yukio Otaguro, Yannis Orginos, Sudhendra Parampalli, Mark Steigerwald, Shriram Gundala, Rambabu Pyapali, Leonard Rarick, Ilyas Elkin, Yuefei Ge, Ishwar Parulkar

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2005

Introduction to the Special Issue on the ISSCC2004.

Georgios K. Konstadinidis, Anantha P. Chandrakasan, Sreedhar Natarajan, Thucydides Xanthopoulos

IEEE J. Solid State Circuits, 2005

2002

Implementation of a third-generation 1.1-GHz 64-bit microprocessor.

Georgios K. Konstadinidis, Kevin Normoyle, Samson Wong, Sutikshan Bhutani, Harry Stuimer, Timothy Johnson, Alan P. Smith, Daniel Y. Cheung, Fabrizio Romano, Shifeng Yu, Sung-Hun Oh, Victor Melamed, Sridhar Narayanan, David Bunsey, Cong Khieu, Kevin J. Wu, Ralf Schmitt, Andy Dumlao, Massimo Sutera, Jade Chau, K. James Lin, William S. Coates

IEEE J. Solid State Circuits, 2002

Timing Window Applications in UltraSPARC-IIIi? Microprocessor Design.

Rita Yu Chen, Paul Yip, Georgios K. Konstadinidis, Andrew Demas, Fabian Klass, Robert E. Mains, Margaret Schmitt, Dina Bistry

Proceedings of the 20th International Conference on Computer Design (ICCD 2002), 2002

1994

Concurrent multipath power delay optimization for high speed digital VLSI systems.

Georgios K. Konstadinidis

PhD thesis, 1994

1992

Optimization of buffer stages in bipolar VLSI systems.

Georgios K. Konstadinidis, Horst H. Berger

IEEE J. Solid State Circuits, July, 1992