Georgios Dimitriou

Orcid: 0000-0002-1726-9044

According to our database1, Georgios Dimitriou authored at least 31 papers between 2000 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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PhD thesis 
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Links

On csauthors.net:

Bibliography

2024
Improved Text Emotion Prediction Using Combined Valence and Arousal Ordinal Classification.
CoRR, 2024

Current Status of Analytical FPGA Placement.
Proceedings of the 9th South-East Europe Design Automation, 2024

Improved Text Emotion Prediction Using Combined Valence and Arousal Ordinal Classification.
Proceedings of the 2024 Conference of the North American Chapter of the Association for Computational Linguistics: Human Language Technologies: Short Papers, 2024

2023
Implementing a Web Application Screener for Preschoolers: Executive Functions and School Readiness.
Int. J. Eng. Pedagog., September, 2023

2022
Low-power Near-data Instruction Execution Leveraging Opcode-based Timing Analysis.
ACM Trans. Archit. Code Optim., 2022

Design Space Exploration of a Sparse MobileNetV2 Using High-Level Synthesis and Sparse Matrix Techniques on FPGAs.
Sensors, 2022

Near Data Processing Performance Improvement Prediction via Metric-Based Workload Classification.
Proceedings of the 11th International Conference on Modern Circuits and Systems Technologies, 2022

The implementation of the flipped classroom model in the teaching of educational robotics: A study in secondary school students.
Proceedings of the IEEE Global Engineering Education Conference, 2022

2021
Juxtaposing Vivado Design Flows in Batch Mode.
Proceedings of the PCI 2021: 25th Pan-Hellenic Conference on Informatics, Volos, Greece, November 26, 2021

Statistical Estimation of Leakage Power Bounds in CMOS VLSI Circuits.
Proceedings of the PCI 2021: 25th Pan-Hellenic Conference on Informatics, Volos, Greece, November 26, 2021

Branchless Code Generation for Modern Processor Architectures.
Proceedings of the PCI 2021: 25th Pan-Hellenic Conference on Informatics, Volos, Greece, November 26, 2021

2020
Global and Pointer Variables in High-Level Synthesis.
Proceedings of the 5th South-East Europe Design Automation, 2020

Low power general purpose loop acceleration for NDP applications.
Proceedings of the PCI 2020: 24th Pan-Hellenic Conference on Informatics, 2020

From Cyber Terrorism to Cyber Peacekeeping: Are we there yet?
Proceedings of the PCI 2020: 24th Pan-Hellenic Conference on Informatics, 2020

Adaptive Operation-Based ALU and FPU Clocking.
Proceedings of the 9th International Conference on Modern Circuits and Systems Technologies, 2020

2019
Instruction-Based Timing Analysis in Pipelined Processors.
Proceedings of the 4th South-East Europe Design Automation, 2019

Multiple Transient Faults in Combinational Logic with Placement Considerations.
Proceedings of the 8th International Conference on Modern Circuits and Systems Technologies, 2019

2018
Resolving Loop Pipelining Issues in the CCC High-level Synthesis E-CAD Framework.
Proceedings of the 41st International Conference on Telecommunications and Signal Processing, 2018

Operation Dependencies in Loop Pipelining for High-Level Synthesis.
Proceedings of the 2018 South-Eastern European Design Automation, 2018

A Placement-Aware Soft Error Rate Estimation of Combinational Circuits for Multiple Transient Faults in CMOS Technology.
Proceedings of the 2018 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, 2018

2017
Placement-based SER estimation in the presence of multiple faults in combinational logic.
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017

Loop pipelining in high-level synthesis with CCC.
Proceedings of the 6th International Conference on Modern Circuits and Systems Technologies, 2017

2016
SER Analysis of Multiple Transient Faults in Combinational Logic.
Proceedings of the SouthEast European Design Automation, 2016

Source-Level Compiler Optimizations for High-Level Synthesis.
Proceedings of the SouthEast European Design Automation, 2016

2015
Performance and power simulation of a functional-unit-network processor with simplescalar and wattch.
Proceedings of the 19th Panhellenic Conference on Informatics, 2015

Hardware synthesis of high-level C constructs.
Proceedings of the 19th Panhellenic Conference on Informatics, 2015

2013
Rapid, low-power loop execution in a network of functional units.
Proceedings of the 17th Panhellenic Conference on Informatics, 2013

2005
Hardware Support for Multithreaded Execution of Loops with Limited Parallelism.
Proceedings of the Advances in Informatics, 2005

A Tool for Calculating Energy Consumption in Wireless Sensor Networks.
Proceedings of the Advances in Informatics, 2005

2004
Loop Scheduling for Multithreaded Processors.
Proceedings of the 2004 International Conference on Parallel Computing in Electrical Engineering (PARELEC 2004), 2004

2000
Loop Scheduling for Multithreaded Processors
PhD thesis, 2000


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