George von Büren

According to our database¹, George von Büren authored at least 8 papers between 2004 and 2009.

Collaborative distances:

Dijkstra number² of five.
Erdős number³ of four.

Timeline

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Article

PhD thesis

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On csauthors.net:

Bibliography

2009

A 5.75 to 44 Gb/s Quarter Rate CDR With Data Rate Selection in 90 nm Bulk CMOS.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

A Low-Power Baseband ASIC for an Energy-Collection IR-UWB Receiver.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2009

Design and phase noise analysis of a multiphase 6 to 11 GHz PLL.

[BibT_eX]

[DOI]

Proceedings of the 35th European Solid-State Circuits Conference, 2009

2008

A T-Coil-Enhanced 8.5 Gb/s High-Swing SST Transmitter in 65 nm Bulk CMOS With ≪ -16 dB Return Loss Over 10 GHz Bandwidth.

[BibT_eX]

[DOI]

IEEE J. Solid State Circuits, 2008

A T-Coil-Enhanced 8.5Gb/s High-Swing source-Series-Terminated Transmitter in 65nm Bulk CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

5.75 to 44Gb/s quarter rate CDR with data rate selection in 90nm bulk CMOS.

[BibT_eX]

[DOI]

Proceedings of the ESSCIRC 2008, 2008

2006

A Combined Dynamic and Static Frequency Divider for a 40GHz PLL in 80nm CMOS.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Solid State Circuits Conference, 2006

2004

BiCMOS Variable Gain LNA at C-Band with Ultra Low Power Consumption for WLAN.

[BibT_eX]

[DOI]

Proceedings of the Telecommunications and Networking, 2004

George von Büren

Timeline

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Links

On csauthors.net:

Bibliography

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