George Theodoridis
Affiliations:- University of Patras, Greece
According to our database1,
George Theodoridis
authored at least 72 papers
between 1996 and 2023.
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Bibliography
2023
Proceedings of the 12th International Conference on Modern Circuits and Systems Technologies, 2023
2022
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
A Multi-stage Hybrid Approach for Mapping Applications on Heterogeneous Multi-core Platforms.
Proceedings of the 30th IFIP/IEEE 30th International Conference on Very Large Scale Integration, 2022
2020
Proceedings of the 28th IFIP/IEEE International Conference on Very Large Scale Integration, 2020
2019
Low-memory and high-performance architectures for the CCSDS 122.0-B-1 compression standard.
Integr., 2019
Proceedings of the 29th International Symposium on Power and Timing Modeling, 2019
2018
Static Mapping of Applications on Heterogeneous Multi-Core Platforms Combining Logic-Based Benders Decomposition with Integer Linear Programming.
ACM Trans. Design Autom. Electr. Syst., 2018
Proceedings of the 41st International Conference on Telecommunications and Signal Processing, 2018
Mapping and Scheduling Hard Real Time Applications on Multicore Systems - The ARGO Approach.
Proceedings of the Applied Reconfigurable Computing. Architectures, Tools, and Applications, 2018
2017
Task graph mapping and scheduling on heterogeneous architectures under communication constraints.
Proceedings of the 2017 International Conference on Embedded Computer Systems: Architectures, 2017
Proceedings of the 27th International Symposium on Power and Timing Modeling, 2017
2016
A Logic-Based Benders Decomposition Approach for Mapping Applications on Heterogeneous Multicore Platforms.
ACM Trans. Embed. Comput. Syst., 2016
Design and implementation of totally-self checking SHA-1 and SHA-256 hash functions' architectures.
Microprocess. Microsystems, 2016
J. Circuits Syst. Comput., 2016
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
2015
A high performance 5 stage pipeline architecture for the H.264/AVC deblocking filter.
Integr., 2015
Proceedings of the 2015 IEEE Computer Society Annual Symposium on VLSI, 2015
40 Gb/s FPGA implementation of a reduced complexity volterra DFE for DQPSK optical links.
Proceedings of the 17th International Conference on Transparent Optical Networks, 2015
Proceedings of the IEEE 5th International Conference on Consumer Electronics - Berlin, 2015
Proceedings of the 23rd European Signal Processing Conference, 2015
2014
On the development of high-throughput and area-efficient multi-mode cryptographic hash designs in FPGAs.
Integr., 2014
IET Comput. Digit. Tech., 2014
Proceedings of the 2014 International Conference on ReConFigurable Computing and FPGAs, 2014
Proceedings of the 18th Panhellenic Conference on Informatics, 2014
Proceedings of the 6th International Symposium on Communications, 2014
A Hybrid ILP-CP Model for Mapping Directed Acyclic Task Graphs to Multicore Architectures.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014
2013
A Systematic Flow for Developing Totally Self-Checking Architectures for SHA-1 and SHA-2 Cryptographic Hash Families.
J. Circuits Syst. Comput., 2013
IET Comput. Digit. Tech., 2013
2012
ACM Trans. Reconfigurable Technol. Syst., 2012
On the Development of Totally Self-checking Hardware Design for the SHA-1 Hash Function.
Proceedings of the SECRYPT 2012, 2012
High-throughput Hardware Architectures of the JH Round-three SHA-3 Candidate - An FPGA Design and Implementation Approach.
Proceedings of the SECRYPT 2012, 2012
2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
2009
The ARISE Approach for Extending Embedded Processors With Arbitrary Hardware Accelerators.
IEEE Trans. Very Large Scale Integr. Syst., 2009
ACM Trans. Reconfigurable Technol. Syst., 2009
IET Comput. Digit. Tech., 2009
2008
Proceedings of the Reconfigurable Computing: Architectures, 2008
2007
Automated framework for partitioning DSP applications in hybrid reconfigurable platforms.
Microprocess. Microsystems, 2007
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
2006
High-Speed FPGA Implementation of Secure Hash Algorithm for IPSec and VPN Applications.
J. Supercomput., 2006
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006
Power Management Through Dynamic Frequency Scaling for Low and Medium Bit-Rate Digital Receivers.
J. Low Power Electron., 2006
An automated development framework for a RISC processor with reconfigurable instruction set extensions.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Enhancing a Reconfigurable Instruction Set Processor with Partial Predication and Virtual Opcode Support.
Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006
2005
Microelectron. J., 2005
A Reconfigurable Coarse-grain Data-path for Accelerating Computational Intensive Kernels.
J. Circuits Syst. Comput., 2005
Des. Autom. Embed. Syst., 2005
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005
A Framework for Partitioning Computational Intensive Applications in Hybrid Reconfigurable Platforms.
Proceedings of the 19th International Parallel and Distributed Processing Symposium (IPDPS 2005), 2005
2004
Des. Autom. Embed. Syst., 2004
An Automated C++ Code and Data Partitioning Framework for Data Management of Data-Intensive Applications.
Proceedings of the Software and Compilers for Embedded Systems, 8th International Workshop, 2004
Proceedings of the Computer Systems: Architectures, 2004
Proceedings of the Integrated Circuit and System Design, 2004
Mapping Computational Intensive Applications to a New Coarse-Grained Reconfigurable Data-Path.
Proceedings of the Integrated Circuit and System Design, 2004
Proceedings of the 2004 11th IEEE International Conference on Electronics, 2004
Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path.
Proceedings of the Field Programmable Logic and Application, 2004
Proceedings of the ACM/SIGDA 12th International Symposium on Field Programmable Gate Arrays, 2004
Accelerating DSP Applications on a Mixed Granularity Platform with a New Reconfigurable Coarse-Grain Data-Path.
Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004
A Partitioning Methodology for Accelerating Applications in Hybrid Reconfigurable Platforms.
Proceedings of the 2004 Design, 2004
2003
An efficient reconfigurable multiplier architecture for Galois field GF(2<sup>m</sup>).
Microelectron. J., 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003
2002
A fast and accurate delay dependent method for switching estimation of large combinational circuits.
J. Syst. Archit., 2002
2001
VLSI Design, 2001
A Probabilistic Power Estimation Method for Combinational Circuits Under Real Gate Delay Model.
VLSI Design, 2001
2000
Reducing Power Consumption through Dynamic Frequency Scaling for a Class of Digital Receivers.
Proceedings of the Integrated Circuit Design, 2000
Proceedings of the Integrated Circuit Design, 2000
Proceedings of the IEEE International Symposium on Circuits and Systems, 2000
1999
Proceedings of the 1999 International Symposium on Circuits and Systems, ISCAS 1999, Orlando, Florida, USA, May 30, 1999
1996
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996
Proceedings of Third International Conference on Electronics, Circuits, and Systems, 1996