George S. Taylor

According to our database, George S. Taylor authored at least 17 papers between 1981 and 2003.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2003

Balanced self-checking asynchronous logic for smart card applications.

Simon W. Moore, Ross J. Anderson, Robert D. Mullins, George S. Taylor, Jacques J. A. Fournier

Microprocess. Microsystems, 2003

Security Evaluation of Asynchronous Circuits.

Jacques J. A. Fournier, Simon W. Moore, Huiyun Li, Robert D. Mullins, George S. Taylor

Proceedings of the Cryptographic Hardware and Embedded Systems, 2003

2002

Point to Point GALS Interconnect.

George S. Taylor, Simon W. Moore, Robert D. Mullins, Peter Robinson

Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

Improving Smart Card Security Using Self-Timed Circuits.

Simon W. Moore, Robert D. Mullins, Paul A. Cunningham, Ross J. Anderson, George S. Taylor

Proceedings of the 8th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2002), 2002

2000

Self-Calibrating Clocks for Globally Asynchronous Locally Synchronous Systems.

Simon W. Moore, George S. Taylor, Paul A. Cunningham, Robert D. Mullins, Peter Robinson

Proceedings of the IEEE International Conference On Computer Design: VLSI In Computers & Processors, 2000

An On-Chip Dynamically Recalibrated Delay Line for Embedded Self-Timed Systems.

George S. Taylor, Simon W. Moore, Steve Wilcox, Peter Robinson

Proceedings of the 6th International Symposium on Advanced Research in Asynchronous Circuits and Systems (ASYNC 2000), 2000

1998

Reduced complexity two-phase micropipeline latch controller.

George S. Taylor, Gerard M. Blair

IEEE J. Solid State Circuits, 1998

1989

A VLSI chip set for a multiprocessor workstation. I. An RISC microprocessor with coprocessor interface and support for symbolic processing.

David D. Lee, Shing I. Kong, Mark D. Hill, George S. Taylor, David A. Hodges, Randy H. Katz, David A. Patterson

IEEE J. Solid State Circuits, December, 1989

1987

Fast multiply and divide for a VLSI floating-point unit.

Bidyut Kumar Bose, Li-fan Pei, George S. Taylor, David A. Patterson

Proceedings of the 8th IEEE Symposium on Computer Arithmetic, 1987

1986

An In-Cache Address Translation Mechanism.

David A. Wood, Susan J. Eggers, Garth A. Gibson, Mark D. Hill, Joan M. Pendleton, Scott A. Ritchie, George S. Taylor, Randy H. Katz, David A. Patterson

Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

Evaluation of the SPUR Lisp Architecture.

George S. Taylor, Paul N. Hilfinger, James R. Larus, David A. Patterson, Benjamin G. Zorn

Proceedings of the 13th Annual Symposium on Computer Architecture, Tokyo, Japan, June 1986, 1986

1985

The Magic VLSI Layout System.

John K. Ousterhout, Gordon T. Hamachi, Robert N. Mayo, Walter S. Scott, George S. Taylor

IEEE Des. Test, 1985

Radix 16 SRT dividers with overlapped quotient selection stages: A 225 nanosecond double precision divider for the S-1 Mark IIB.

George S. Taylor

Proceedings of the 7th IEEE Symposium on Computer Arithmetic, 1985

1984

Magic's incremental design-rule checker.

George S. Taylor, John K. Ousterhout

Proceedings of the 21st Design Automation Conference, 1984

1983

Arithmetic on the ELXSI System 6400.

George S. Taylor

Proceedings of the 6th IEEE Symposium on Computer Arithmetic, 1983

1981

VAX hardware for the proposed IEEE floating-point standard.

George S. Taylor, David A. Patterson

Proceedings of the 5th IEEE Symposium on Computer Arithmetic, 1981

Compatible hardware for division and square root.

George S. Taylor

Proceedings of the 5th IEEE Symposium on Computer Arithmetic, 1981