George Kurian

Orcid: 0000-0002-3478-518X

Affiliations:
  • Google, Mountain View, CA, USA
  • Massachusetts Institute of Technology, Cambridge, MA, USA (PhD 2015)


According to our database1, George Kurian authored at least 26 papers between 1995 and 2024.

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Timeline

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Bibliography

2024
Navigating the Docker Ecosystem: A Comprehensive Taxonomy and Survey.
CoRR, 2024

A Latent Dirichlet Allocation (LDA) Semantic Text Analytics Approach to Explore Topical Features in Charity Crowdfunding Campaigns.
CoRR, 2024

2023
Risk of AI in Healthcare: A Comprehensive Literature Review and Study Framework.
CoRR, 2023

TPU v4: An Optically Reconfigurable Supercomputer for Machine Learning with Hardware Support for Embeddings.
Proceedings of the 50th Annual International Symposium on Computer Architecture, 2023

2021
The Design Process for Google's Training Chips: TPUv2 and TPUv3.
IEEE Micro, 2021

Ten Lessons From Three Generations Shaped Google's TPUv4i : Industrial Product.
Proceedings of the 48th ACM/IEEE Annual International Symposium on Computer Architecture, 2021

2020
A domain-specific supercomputer for training deep neural networks.
Commun. ACM, 2020

Google's Training Chips Revealed: TPUv2 and TPUv3.
Proceedings of the IEEE Hot Chips 32 Symposium, 2020

2017
Predict Florida Tourism Trend via Using Data Mining Techniques.
Proceedings of the Practice and Experience in Advanced Research Computing 2017: Sustainability, 2017

2016
Locality-aware data replication in the last-level cache for large scale multicores.
J. Supercomput., 2016

LDAC: Locality-Aware Data Access Control for Large-Scale Multicore Cache Hierarchies.
ACM Trans. Archit. Code Optim., 2016

Google's Neural Machine Translation System: Bridging the Gap between Human and Machine Translation.
CoRR, 2016

2015
Locality-aware cache hierarchy management for multicore processors.
PhD thesis, 2015

OSPREY: Implementation of Memory Consistency Models for Cache Coherence Protocols involving Invalidation-Free Data Access.
Proceedings of the 2015 International Conference on Parallel Architectures and Compilation, 2015

2014
Power modeling and other new features in the Graphite simulator.
Proceedings of the 2014 IEEE International Symposium on Performance Analysis of Systems and Software, 2014

Author retrospective for analytical cache models with applications to cache partitioning.
Proceedings of the ACM International Conference on Supercomputing 25th Anniversary Volume, 2014

Locality-aware data replication in the Last-Level Cache.
Proceedings of the 20th IEEE International Symposium on High Performance Computer Architecture, 2014

2013
The locality-aware adaptive cache coherence protocol.
Proceedings of the 40th Annual International Symposium on Computer Architecture, 2013

2012
DSENT - A Tool Connecting Emerging Photonics with Electronics for Opto-Electronic Networks-on-Chip Modeling.
Proceedings of the 2012 Sixth IEEE/ACM International Symposium on Networks-on-Chip (NoCS), 2012

Cross-layer Energy and Performance Evaluation of a Nanophotonic Manycore Processor System Using Real Application Workloads.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium, 2012

Self-aware computing in the Angstrom processor.
Proceedings of the 49th Annual Design Automation Conference 2012, 2012

2010
ATAC: Improving performance and programmability with on-chip optical networks.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Graphite: A distributed parallel simulator for multicores.
Proceedings of the 16th International Conference on High-Performance Computer Architecture (HPCA-16 2010), 2010

ATAC: a 1000-core cache-coherent processor with on-chip optical network.
Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques, 2010

2009
Test Power Reduction Using Integrated Scan Cell and Test Vector Reordering Techniques on Linear Scan and Double Tree Scan Architectures.
J. Low Power Electron., 2009

1995
People Oriented Software Technology, and its Use in Environmental Reporting
Proceedings of the Database and Expert Systems Applications, 1995


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