George Kornaros

This page is a disambiguation page, it actually contains mutiple papers from persons of the same or a similar name.

Bibliography

2024
Flexible Updating of Internet of Things Computing Functions through Optimizing Dynamic Partial Reconfiguration.
ACM Trans. Embed. Comput. Syst., March, 2024

From Cloud to IoT Device Authenticity under Kubernetes Management.
Proceedings of the 11th International Conference on Internet of Things: Systems, 2024

2023
Managing Concurrent Queues for Efficient In- Vehicle Gateways.
J. Commun., May, 2023

Energy Efficient Deep-Edge Computing through Hardware Machine Learning.
Proceedings of the 9th IEEE World Forum on Internet of Things, 2023

Quantum-Secure Communication for Trusted Edge Computing with IoT Devices.
Proceedings of the ICT Systems Security and Privacy Protection, 2023

Smart Manufacturing Maintenance through LoRaWAN-based Ecosystem.
Proceedings of the IEEE International Mediterranean Conference on Communications and Networking, 2023

Digital Twins for Remote ECG Monitoring.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2023

2022
Hardware-Assisted Machine Learning in Resource-Constrained IoT Environments for Security: Review and Future Prospective.
IEEE Access, 2022

Software-defined hardware-assisted isolation for trusted next-generation IoT systems.
Proceedings of the SAC '22: The 37th ACM/SIGAPP Symposium on Applied Computing, Virtual Event, April 25, 2022

Poster: Secure Multi-tenant Provisioning of IoT Devices by Combining On-chip Cortex-M TrustZone with Secure Element.
Proceedings of the 2022 International Conference on Embedded Wireless Systems and Networks, 2022

Towards Efficient Gateways and Servers for Biosensors.
Proceedings of the Applications in Electronics Pervading Industry, Environment and Society, 2022

2021
Secure Asset Tracking in Manufacturing through Employing IOTA Distributed Ledger Technology.
Proceedings of the 21st IEEE/ACM International Symposium on Cluster, 2021

2020
Efficient Job Offloading in Heterogeneous Systems Through Hardware-Assisted Packet-Based Dispatching and User-Level Runtime Infrastructure.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Towards holistic secure networking in connected vehicles through securing CAN-bus communication and firmware-over-the-air updating.
J. Syst. Archit., 2020

Automotive Virtual In-sensor Analytics for Securing Vehicular Communication.
IEEE Des. Test, 2020

RSMCC: Enabling Ring-based Software Managed Cache-Coherent Embedded SoCs.
Proceedings of the 28th Euromicro International Conference on Parallel, 2020

2019
TrustNet: Ensuring Normal-world and Trusted-world CAN-bus Networking.
Proceedings of the 2019 IEEE International Conference on Communications, 2019

Secure over-the-air firmware updating for automotive electronic control units.
Proceedings of the 34th ACM/SIGAPP Symposium on Applied Computing, 2019

2018
Energy-Performance Considerations for Data Offloading to FPGA-Based Accelerators Over PCIe.
ACM Trans. Archit. Code Optim., 2018

Hardware-Assisted Security in Electronic Control Units: Secure Automotive Communications by Utilizing One-Time-Programmable Network on Chip and Firewalls.
IEEE Micro, 2018

Enabling Efficient Job Dispatching in Accelerator-Extended Heterogeneous Systems with Unified Address Space.
Proceedings of the 30th International Symposium on Computer Architecture and High Performance Computing, 2018

2017
Towards architectural support for bandwidth management in mixed-critical embedded systems.
SIGBED Rev., 2017

Securing Dynamic Firmware Updates of Mixed-Critical Applications.
Proceedings of the 3rd IEEE International Conference on Cybernetics, 2017

2016
Adaptive memory management scheme for MMU-less embedded systems.
Proceedings of the 11th IEEE Symposium on Industrial Embedded Systems, 2016

VWQS: A dispatching mechanism of variable-size tasks in heterogeneous systems.
Proceedings of the International Conference on High Performance Computing & Simulation, 2016

Towards Trusted Apps platforms for open CPS.
Proceedings of the 3rd International Workshop on Emerging Ideas and Trends in Engineering of Cyber-Physical Systems, 2016

2015
Security in MPSoCs: A NoC Firewall and an Evaluation Framework.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2015

High-level security services based on a hardware NoC Firewall module.
Proceedings of the 12th International Workshop on Intelligent Solutions in Embedded Systems, 2015

Load balancing, broadcast, and scatter primitives for efficient multicore applications.
Proceedings of the 12th International Workshop on Intelligent Solutions in Embedded Systems, 2015

Dithering-Based Power and Thermal Management on FPGA-Based Multi-core Embedded Systems.
Proceedings of the 13th IEEE International Conference on Embedded and Ubiquitous Computing, 2015

TAPPS - Trusted Apps for Open Cyber-Physical Systems.
Proceedings of the E-Democracy - Citizen Rights in the World of the New Computing Paradigms, 2015

Hardware Support for Cost-Effective System-Level Protection in Multi-core SoCs.
Proceedings of the 2015 Euromicro Conference on Digital System Design, 2015

2014
Dynamic Power and Thermal Management of NoC-Based Heterogeneous MPSoCs.
ACM Trans. Reconfigurable Technol. Syst., 2014

I/O virtualization utilizing an efficient hardware system-level Memory Management Unit.
Proceedings of the 2014 International Symposium on System-on-Chip, 2014

Security Effectiveness and a Hardware Firewall for MPSoCs.
Proceedings of the 2014 IEEE International Conference on High Performance Computing and Communications, 2014

Runtime Adaptation of Embedded Tasks with A-Priori Known Timing Behavior Utilizing On-Line Partner-Core Monitoring and Recovery.
Proceedings of the 12th IEEE International Conference on Embedded and Ubiquitous Computing, 2014

SAVE: Towards Efficient Resource Management in Heterogeneous System Architectures.
Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013
A survey and taxonomy of on-chip monitoring of multicore systems-on-chip.
ACM Trans. Design Autom. Electr. Syst., 2013

High-Speed Hardware Arbitration Supporting Priorities and Bounded Service Latency.
IEEE Embed. Syst. Lett., 2013

Monitoring-Aware Virtual Platform Prototype of Heterogeneous NoC-Based Multicore SoCs.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

Non-intrusive NoC DFS for Soft Real-Time Multimedia Applications.
Proceedings of the 2013 Euromicro Conference on Digital System Design, 2013

From embedded multi-core SoCs to scale-out processors.
Proceedings of the Design, Automation and Test in Europe, 2013

2012
Real-Time Monitoring of Multicore SoCs through Specialized Hardware Agents on NoC Network Interfaces.
Proceedings of the 26th IEEE International Parallel and Distributed Processing Symposium Workshops & PhD Forum, 2012

An automated infrastructure for real-time monitoring of multi-core Systems-on-Chip.
Proceedings of the IEEE 15th International Symposium on Design and Diagnostics of Electronic Circuits & Systems, 2012

Towards Full Virtualization of Heterogeneous NoC-based Multicore Embedded Architectures.
Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

2011
Energy Efficient Data Transmission of On-Chip Serial Links - A Case Study.
Proceedings of the Solutions on Embedded Systems, 2011

Dynamic resource management in modern multicore SoCs by exposing NoC services.
Proceedings of the 6th International Workshop on Reconfigurable Communication-centric Systems-on-Chip, 2011

Hardware-assisted dynamic power and thermal management in multi-core SoCs.
Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

Power-Aware Multicore SoC and NoC Design.
Proceedings of the Multiprocessor System-on-Chip - Hardware Design and Tool Integration., 2011

2010
Design and implementation of high-speed buffered crossbars with efficient load balancing for multi-core SoCs.
Microprocess. Microsystems, 2010

A soft multi-core architecture for edge detection and data analysis of microarray images.
J. Syst. Archit., 2010

NCXplore: a design space exploration framework of temporal encoding for on-chip serial interconnects.
Int. J. High Perform. Syst. Archit., 2010

On Scaling Speedup with Coarse-Grain Coprocessor Accelerators on Reconfigurable Platforms.
Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

2009
Temporal coding schemes for energy efficient data transmission in Systems-on-Chip.
Proceedings of the Seventh Workshop on Intelligent solutions in Embedded Systems, 2009

2008
Microarchitecture of a MultiCore SoC for Data Analysis of a Lab-on-Chip Microarray.
EURASIP J. Adv. Signal Process., 2008

Architecture and implementation of a Frame Aggregation Unit for optical frame-based switching.
Proceedings of the FPL 2008, 2008

2007
An Embedded Networking SoC for purely Ethernet MANs/WANs.
Proceedings of the 12th IEEE Symposium on Computers and Communications (ISCC 2007), 2007

A buffered crossbar-based chip interconnection framework supporting quality of service.
Proceedings of the 17th ACM Great Lakes Symposium on VLSI 2007, 2007

2006
BCB: A Buffered CrossBar Switch Fabric Utilizing Shared Memory.
Proceedings of the Ninth Euromicro Conference on Digital System Design: Architectures, Methods and Tools (DSD 2006), 30 August, 2006

2005
Queue Management in Network Processors.
Proceedings of the 2005 Design, 2005

2004
PRO3: A Hybrid NPU Architecture.
IEEE Micro, 2004

An FPGA-based queue management system for high speed networking devices.
Microprocess. Microsystems, 2004

Software Processing Performance in Network Processors.
Proceedings of the 2004 Design, 2004

2003
Processing and Scheduling Components in an Innovative Network Processor Architecture.
Proceedings of the 16th International Conference on VLSI Design (VLSI Design 2003), 2003

An innovative scheduling scheme for high-speed network processors.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Active flow identifiers for scalable, QoS scheduling in 10-Gbps network processors.
Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

Performance against cost trade-offs for hardware compression in 10 Gigabit networks.
Proceedings of the 2003 10th IEEE International Conference on Electronics, 2003

An Innovative Resource Management Scheme for Multi-gigabit Networking Systems.
Proceedings of the High Speed Networks and Multimedia Communications, 2003

An Efficient Implementation of Fair Load Balancing over Multi-CPU SOC Architectures.
Proceedings of the 2003 Euromicro Symposium on Digital Systems Design (DSD 2003), 2003

A fully-programmable memory management system optimizing queue handling at multi-gigabit rates.
Proceedings of the 40th Design Automation Conference, 2003

GFS: An Efficient Implementation of Fair Scheduling for Mult-Gigabit Packet Networks.
Proceedings of the 14th IEEE International Conference on Application-Specific Systems, 2003

1999
ATLAS I: implementing a single-chip ATM switch with backpressure.
IEEE Micro, 1999

1997
Pipelined Multi-Queue Management in a VLSI ATM Switch Chip with Credit-Based Flow-Control.
Proceedings of the 17th Conference on Advanced Research in VLSI (ARVLSI '97), 1997


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