George Economakos
According to our database1,
George Economakos
authored at least 85 papers
between 1995 and 2016.
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Bibliography
2016
ACM Trans. Embed. Comput. Syst., 2016
An Integrated Exploration and Virtual Platform Framework for Many-Accelerator Heterogeneous Systems.
ACM Trans. Embed. Comput. Syst., 2016
An OpenCL-based framework for rapid virtual prototyping of heterogeneous architectures.
Proceedings of the International Conference on Embedded Computer Systems: Architectures, 2016
2015
A virtual platform for exploring hierarchical interconnection for many-accelerator systems.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
A power estimation technique for cycle-accurate higher-abstraction SystemC-based CPU models.
Proceedings of the 2015 International Conference on Embedded Computer Systems: Architectures, 2015
Comparison of OpenCL based design for a medical device on heterogeneous architectures with CPU, GPU and FPGA.
Proceedings of the 19th Panhellenic Conference on Informatics, 2015
Using advanced FPGA SoC technologies for the design of industrial control applications.
Proceedings of the 6th International Conference on Information, 2015
Performance improvements in a modern hardware design environment for control applications.
Proceedings of the IEEE International Conference on Industrial Technology, 2015
Rapid prototyping and Design Space Exploration methodologies for many-accelerator systems.
Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015
Evaluation of High-Level Synthesis Techniques for Memory and Datapath Tradeoffs in FPGA Based SoC Architectures.
Proceedings of the Applied Reconfigurable Computing - 11th International Symposium, 2015
2014
ACM Trans. Embed. Comput. Syst., 2014
Microprocess. Microsystems, 2014
Systematic Design and Evaluation of Reconfigurable Arithmetic Components in the Deep submicron Domain.
J. Circuits Syst. Comput., 2014
Proceedings of the XIVth International Conference on Embedded Computer Systems: Architectures, 2014
Hardware accelerated rician denoise algorithm for high performance magnetic resonance imaging.
Proceedings of the 4th International Conference on Wireless Mobile Communication and Healthcare: "Transforming healthcare through innovations in mobile and wireless technologies", 2014
A scalable FPGA-based architecture for digital controllers and a corresponding rapid prototyping design methodology.
Proceedings of the 23rd IEEE International Symposium on Industrial Electronics, 2014
Program-based and Model-based PLC Design Environment for Multicore FPGA Architectures.
Proceedings of the ICINCO 2014 - Proceedings of the 11th International Conference on Informatics in Control, Automation and Robotics, Volume 1, Vienna, Austria, 1, 2014
Proceedings of the 21st IEEE International Conference on Electronics, Circuits and Systems, 2014
Effective Platform-Level Exploration for Heterogeneous Multicores Exploiting Simulation-Induced Slacks.
Proceedings of the 5th Workshop on Parallel Programming and Run-Time Management Techniques for Many-core Architectures and the 3rd Workshop on Design Tools and Architectures for Multicore Embedded Computing Platforms, 2014
2013
Proceedings of the 2013 International Conference on Embedded Computer Systems: Architectures, 2013
A new design paradigm for floating point DSP applications based on ESL/HLS and FPGAs?
Proceedings of the IEEE International Symposium on Signal Processing and Information Technology, 2013
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013
Rapid prototyping of digital controllers using FPGAs and ESL/HLS design methodologies.
Proceedings of the 2013 19th International Conference on Automation and Computing, 2013
Proceedings of the 13th IEEE International Conference on BioInformatics and BioEngineering, 2013
2012
Compiler-in-the-loop exploration during datapath synthesis for higher quality delay-area trade-offs.
ACM Trans. Design Autom. Electr. Syst., 2012
Systematic design and evaluation of a scalable reconfigurable multiplier scheme for HLS environments.
Proceedings of the 7th International Workshop on Reconfigurable and Communication-Centric Systems-on-Chip (ReCoSoC), 2012
Proceedings of the 16th Panhellenic Conference on Informatics, PCI 2012, 2012
A Methodology for Efficient Use of OpenCL, ESL and FPGAs in Multi-core Architectures.
Proceedings of the Euro-Par 2012: Parallel Processing Workshops, 2012
Power Optimization Opportunities for a Reconfigurable Arithmetic Component in the Deep Submicron Domain.
Proceedings of the 15th Euromicro Conference on Digital System Design, 2012
2011
IEEE Trans. Very Large Scale Integr. Syst., 2011
Proceedings of the 2011 International Conference on Reconfigurable Computing and FPGAs, 2011
Proceedings of the 18th IEEE International Conference on Electronics, Circuits and Systems, 2011
2010
Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation, 2010
Efficient High Level Synthesis Exploration Methodology Combining Exhaustive and Gradient-Based Pruned Searching.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
A High Level Synthesis Exploration Framework with Iterative Design Space Partitioning.
Proceedings of the VLSI 2010 Annual Symposium - Selected papers, 2010
High-Level Synthesis Methodologies for Delay-Area Optimized Coarse-Grained Reconfigurable Coprocessor Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Systematic Exploration of Energy-Efficient Application-Specific Network-on-Chip Architectures.
Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010
Designing efficient DSP datapaths through compiler-in-the-loop exploration methodology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010
Proceedings of the 17th IEEE International Conference on Electronics, 2010
Proceedings of the Design, Automation and Test in Europe, 2010
2009
Extending an embedded RISC microprocessor for efficient translation based Java execution.
Microprocess. Microsystems, 2009
Designing coarse-grain reconfigurable architectures by inlining flexibility into custom arithmetic data-paths.
Integr., 2009
Proceedings of the 23rd IEEE International Symposium on Parallel and Distributed Processing, 2009
A design methodology for high-performance and low-leakage fixed-point transpose FIR filters.
Proceedings of the 16th IEEE International Conference on Electronics, 2009
Three dimensional FPGA architectures: A shift paradigm for energy-performance efficient DSP implementations.
Proceedings of the 16th International Conference on Digital Signal Processing, 2009
Architectural exploration in biomedical hardware design using a novel behavioral synthesis methodology.
Proceedings of the 17th European Signal Processing Conference, 2009
Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis.
Proceedings of the 12th Euromicro Conference on Digital System Design, 2009
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2009
2008
J. Syst. Archit., 2008
Proceedings of the 2008 International Conference on Embedded Computer Systems: Architectures, 2008
A flexible architecture for DSP applications combining high performance arithmetic with small scale configurability.
Proceedings of the 2008 16th European Signal Processing Conference, 2008
Efficient serial and parallel implementation of programmable fir filters based on the merging technique.
Proceedings of the 2008 16th European Signal Processing Conference, 2008
Optimized FPGA implementations of demanding PLC programs based on hardware high-level synthesis.
Proceedings of 13th IEEE International Conference on Emerging Technologies and Factory Automation, 2008
A Scheduling Postprocessor to Exploit Morphable RTL Components During High-Level Synthesis.
Proceedings of the 11th Euromicro Conference on Digital System Design: Architectures, 2008
Efficient implementation of biomedical hardware using open source descriptions and behavioral synthesis.
Proceedings of the 8th IEEE International Conference on Bioinformatics and Bioengineering, 2008
Mapping DSP Applications onto High-Performance Architectural Templates with Inlined Flexibility.
Proceedings of the NASA/ESA Conference on Adaptive Hardware and Systems, 2008
2007
Flexibility Inlining into Arithmetic Data-paths Exploiting A Regular Interconnection Scheme.
Proceedings of the 2007 International Conference on Embedded Computer Systems: Architectures, 2007
Run-time reconfigurable solutions for adaptive control applications.
Proceedings of the ICINCO 2007, 2007
Power-Efficient and Low Latency Implementation of Programmable FIR filters Using Carry-Save Arithmetic.
Proceedings of the 14th IEEE International Conference on Electronics, 2007
A regular interconnection scheme for efficient mapping of DSP kernels into reconfigurable hardware.
Proceedings of the 15th European Signal Processing Conference, 2007
Proceedings of the 15th European Signal Processing Conference, 2007
Proceedings of the 15th European Signal Processing Conference, 2007
Proceedings of the Second NASA/ESA Conference on Adaptive Hardware and Systems (AHS 2007), 2007
2006
Proceedings of the 4th international workshop on Java technologies for real-time and embedded systems, 2006
Bit level architectural exploration technique for the design of low power multipliers.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006
Proceedings of the 13th IEEE International Conference on Electronics, 2006
2005
Proceedings of the 12th IEEE International Conference on Electronics, 2005
2002
Handling advanced scheduling heuristics under a hardware compiler generation environment.
Knowl. Based Syst., 2002
2001
Proceedings of the Euromicro Symposium on Digital Systems Design 2001 (Euro-DSD 2001), 2001
Proceedings of the Conference on Design, Automation and Test in Europe, 2001
2000
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
A complete specification and implementation methodology for high-level hardware transformations.
Proceedings of the 2000 7th IEEE International Conference on Electronics, 2000
1999
Proceedings of the 6th IEEE International Conference on Electronics, Circuits and Systems, 1999
Proceedings of the 25th EUROMICRO '99 Conference, 1999
Proceedings of the Correct Hardware Design and Verification Methods, 1999
1998
Proceedings of the 1998 ACM symposium on Applied Computing, 1998
Proceedings of the 9th European Signal Processing Conference, 1998
Exploiting the Use of VHDL Specifications in the AGENDA High-Level Synthesis Environment.
Proceedings of the 24th EUROMICRO '98 Conference, 1998
AGENDA: An Attribute Grammar Driven Environment for the Design Automation of Digital Systems.
Proceedings of the 1998 Design, 1998
1997
Proceedings of the High-Performance Computing and Networking, 1997
Hardware compilation using attribute grammars.
Proceedings of the Advances in Hardware Design and Verification, 1997
1995
Inf. Softw. Technol., 1995