George A. Constantinides

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., December, 2024

QERA: an Analytical Framework for Quantization Error Reconstruction.

[BibT_eX]

[DOI]

Cheng Zhang

Jeffrey T. H. Wong

Can Xiao

CoRR, 2024

Optimised Grouped-Query Attention Mechanism for Transformers.

[BibT_eX]

[DOI]

CoRR, 2024

Unlocking the Global Synergies in Low-Rank Adapters.

[BibT_eX]

[DOI]

CoRR, 2024

LQER: Low-Rank Quantization Error Reconstruction for LLMs.

[BibT_eX]

[DOI]

Cheng Zhang

George Anthony Constantinides

Proceedings of the Forty-first International Conference on Machine Learning, 2024

Soft GPGPU versus IP cores: Quantifying and Reducing the Performance Gap.

[BibT_eX]

[DOI]

Martin Langhammer

Proceedings of the 14th International Symposium on Highly Efficient Accelerators and Reconfigurable Technologies, 2024

Automated Feature Testing of Verilog Parsers using Fuzzing (Registered Report).

[BibT_eX]

[DOI]

Quentin Corradi

Proceedings of the 3rd ACM International Fuzzing Workshop, 2024

Exploring FPGA designs for MX and beyond.

[BibT_eX]

[DOI]

Ebby Samson

Naveen Mellempudi

Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

NeuraLUT: Hiding Neural Network Density in Boolean Synthesizable Functions.

[BibT_eX]

[DOI]

Marta Andronic

Proceedings of the 34th International Conference on Field-Programmable Logic and Applications, 2024

A Statically and Dynamically Scalable Soft GPGPU.

[BibT_eX]

[DOI]

Martin Langhammer

Proceedings of the 2024 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2024

Combining Power and Arithmetic Optimization via Datapath Rewriting.

[BibT_eX]

[DOI]

Emiliano Morini

Proceedings of the 31st IEEE Symposium on Computer Arithmetic, 2024

2023

Logic Shrinkage: Learned Connectivity Sparsification for LUT-Based Neural Networks.

[BibT_eX]

[DOI]

Marie Auffret

Georgios-Ilias Stavrou

Mohamed S. Abdelfattah

ACM Trans. Reconfigurable Technol. Syst., December, 2023

Parallelising Control Flow in Dynamic-scheduling High-level Synthesis.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., December, 2023

Enabling Binary Neural Network Training on the Edge.

[BibT_eX]

[DOI]

ACM Trans. Embed. Comput. Syst., November, 2023

Balancing Static Islands in Dynamically Scheduled Circuits Using Continuous Petri Nets.

[BibT_eX]

[DOI]

Estíbaliz Fraca

IEEE Trans. Computers, November, 2023

Horizon-Independent Preconditioner Design for Linear Predictive Control.

[BibT_eX]

[DOI]

IEEE Trans. Autom. Control., 2023

Combining E-Graphs with Abstract Interpretation.

[BibT_eX]

[DOI]

Proceedings of the 12th ACM SIGPLAN International Workshop on the State Of the Art in Program Analysis, 2023

FPGA Resource-aware Structured Pruning for Real-Time Neural Networks.

[BibT_eX]

[DOI]

Benjamin Ramhorst

Vladimir Loncar

Proceedings of the International Conference on Field Programmable Technology, 2023

PolyLUT: Learning Piecewise Polynomials for Ultra-Low Latency FPGA LUT-based Inference.

[BibT_eX]

[DOI]

Marta Andronic

Proceedings of the International Conference on Field Programmable Technology, 2023

eGPU: A 750 MHz Class Soft GPGPU for FPGA.

[BibT_eX]

[DOI]

Martin Langhammer

Proceedings of the 33rd International Conference on Field-Programmable Logic and Applications, 2023

Datapath Verification via Word-Level E-Graph Rewriting.

[BibT_eX]

[DOI]

Proceedings of the Formal Methods in Computer-Aided Design, 2023

ATHEENA: A Toolflow for Hardware Early-Exit Network Automation.

[BibT_eX]

[DOI]

Benjamin Biggs

Proceedings of the 31st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2023

Revisiting Block-based Quantisation: What is Important for Sub-8-bit LLM Inference?

[BibT_eX]

[DOI]

Cheng Zhang

Ilia Shumailov

Proceedings of the 2023 Conference on Empirical Methods in Natural Language Processing, 2023

Multi-Metric SMT-Based Evaluation of Worst-Case-Error for Approximate Circuits.

[BibT_eX]

[DOI]

Morteza Rezaalipour

Lorenzo Ferretti

Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

A Parametrizable Template for Approximate Logic Synthesis.

[BibT_eX]

[DOI]

Morteza Rezaalipour

Marco Biasion

Proceedings of the 53rd Annual IEEE/IFIP International Conference on Dependable Systems and Networks, 2023

Automating Constraint-Aware Datapath Optimization using E-Graphs.

[BibT_eX]

[DOI]

Proceedings of the 60th ACM/IEEE Design Automation Conference, 2023

ErrorEval: an Open-Source Worst-Case-Error Evaluation Framework for Approximate Computing.

[BibT_eX]

[DOI]

Morteza Rezaalipour

Lorenzo Ferretti

Proceedings of the 20th ACM International Conference on Computing Frontiers, 2023

Multiplier Optimization via E-Graph Rewriting.

[BibT_eX]

[DOI]

Andy Wanna

Milos D. Ercegovac

Proceedings of the 57th Asilomar Conference on Signals, Systems, and Computers, ACSSC 2023, Pacific Grove, CA, USA, October 29, 2023

2022

Generated Data for the Manuscript "Nonideality-Aware Training for Accurate and Robust Low-Power Memristive Neural Networks".

[BibT_eX]

[DOI]

Dovydas Joksas

Nikolaos Barmpatsalos

Wing H. Ng

Anthony J. Kenyon

Adnan Mehonic

Dataset, March, 2022

A Case for Precise, Fine-Grained Pointer Synthesis in High-Level Synthesis.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2022

A Formal Framework for Maximum Error Estimation in Approximate Logic Synthesis.

[BibT_eX]

[DOI]

Giovanni Ansaloni

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

DASS: Combining Dynamic & Static Scheduling in High-Level Synthesis.

[BibT_eX]

[DOI]

Paolo Ienne

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Efficient Memory Arbitration in High-Level Synthesis From Multi-Threaded Code.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2022

Abstract Interpretation on E-Graphs.

[BibT_eX]

[DOI]

CoRR, 2022

High-level Synthesis using the Julia Language.

[BibT_eX]

[DOI]

Benjamin Biggs

CoRR, 2022

MIDAS: Mutual Information Driven Approximate Synthesis.

[BibT_eX]

[DOI]

Sina Boroumand

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2022

Area-Efficient Memory Scheduling for Dynamically Scheduled High-Level Synthesis.

[BibT_eX]

[DOI]

Xuefei He

Proceedings of the International Conference on Field-Programmable Technology, 2022

POLSCA: Polyhedral High-Level Synthesis with Compiler Transformations.

[BibT_eX]

[DOI]

Ruizhe Zhao

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Dynamic Inter-Block Scheduling for HLS.

[BibT_eX]

[DOI]

Proceedings of the 32nd International Conference on Field-Programmable Logic and Applications, 2022

Logic Shrinkage: Learned FPGA Netlist Sparsity for Efficient Neural Network Inference.

[BibT_eX]

[DOI]

Georgios-Ilias Stavrou

Mohamed S. Abdelfattah

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

Finding and Finessing Static Islands in Dynamically Scheduled Circuits.

[BibT_eX]

[DOI]

Proceedings of the FPGA '22: The 2022 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, Virtual Event, USA, 27 February 2022, 2022

Dynamic C-Slow Pipelining for HLS.

[BibT_eX]

[DOI]

Proceedings of the 30th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2022

Automatic Datapath Optimization using E-Graphs.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Symposium on Computer Arithmetic, 2022

2021

Generated Data for the Manuscript "Nonideality-Aware Training for Accurate and Robust Low-Power Memristive Neural Networks".

[BibT_eX]

[DOI]

Dovydas Joksas

Nikolaos Barmpatsalos

Wing H. Ng

Anthony J. Kenyon

Adnan Mehonic

Dataset, December, 2021

Global Analysis of C Concurrency in High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2021

Digit Stability Inference for Iterative Methods Using Redundant Number Representation.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2021

Nonideality-Aware Training for Accurate and Robust Low-Power Memristive Neural Networks.

[BibT_eX]

[DOI]

Dovydas Joksas

Nikolaos Barmpatsalos

Wing H. Ng

Anthony J. Kenyon

Adnan Mehonic

CoRR, 2021

Enabling Binary Neural Network Training on the Edge.

[BibT_eX]

[DOI]

CoRR, 2021

Exploiting the Correlation between Dependence Distance and Latency in Loop Pipelining for HLS.

[BibT_eX]

[DOI]

Proceedings of the 31st International Conference on Field-Programmable Logic and Applications, 2021

Probabilistic Optimization for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the FPGA '21: The 2021 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, Virtual Event, USA, February 28, 2021

Probabilistic Scheduling in High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2021

Rigorous Roundoff Error Analysis of Probabilistic Floating-Point Computations.

[BibT_eX]

[DOI]

Fredrik Dahlqvist

Zvonimir Rakamaric

Rocco Salvia

Proceedings of the Computer Aided Verification - 33rd International Conference, 2021

Learning Boolean Circuits from Examples for Approximate Logic Synthesis.

[BibT_eX]

[DOI]

Sina Boroumand

Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020

architect: Arbitrary-Precision Hardware With Digit Elision for Efficient Iterative Compute.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2020

LUTNet: Learning FPGA Configurations for Highly Efficient Neural Network Inference.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2020

Approximate Logic Synthesis: A Survey.

[BibT_eX]

[DOI]

Giovanni Ansaloni

Sherief Reda

Proc. IEEE, 2020

Precise Pointer Analysis in High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 30th International Conference on Field-Programmable Logic and Applications, 2020

Combining Dynamic & Static Scheduling in High-level Synthesis.

[BibT_eX]

[DOI]

Paolo Ienne

Proceedings of the FPGA '20: The 2020 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2020

2019

Automatic Software and Computing Hardware Codesign for Predictive Control.

[BibT_eX]

[DOI]

IEEE Trans. Control. Syst. Technol., 2019

Calculated Risks: Quantifying Timing Error Probability With Extended Static Timing Analysis.

[BibT_eX]

[DOI]

Kevin E. Murray

Vaughn Betz

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2019

Deep Neural Network Approximation for Custom Hardware: Where We've Been, Where We're Going.

[BibT_eX]

[DOI]

ACM Comput. Surv., 2019

Rethinking Arithmetic for Deep Neural Networks.

[BibT_eX]

[DOI]

CoRR, 2019

Bounding Computational Complexity under Cost Function Scaling in Predictive Control.

[BibT_eX]

[DOI]

CoRR, 2019

Automatic Generation of Multi-Precision Multi-Arithmetic CNN Accelerators for FPGAs.

[BibT_eX]

[DOI]

Cheng-Zhong Xu

Proceedings of the International Conference on Field-Programmable Technology, 2019

Accelerated Approximate Nearest Neighbors Search Through Hierarchical Product Quantization.

[BibT_eX]

[DOI]

Ameer M. S. Abdelhadi

Proceedings of the International Conference on Field-Programmable Technology, 2019

EASY: Efficient Arbiter SYnthesis from Multi-threaded Code.

[BibT_eX]

[DOI]

Proceedings of the 2019 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2019

LUTNet: Rethinking Inference in FPGA Soft Logic.

[BibT_eX]

[DOI]

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Formalizing Loop-Carried Dependencies in Coq for High-Level Synthesis.

[BibT_eX]

[DOI]

Florian Faissole

Proceedings of the 27th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2019

Partition and Propagate: an Error Derivation Algorithm for the Design of Approximate Circuits.

[BibT_eX]

[DOI]

Giovanni Ansaloni

Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Modeling Round-off Error in the Fast Gradient Method for Predictive Control.

[BibT_eX]

[DOI]

Proceedings of the 58th IEEE Conference on Decision and Control, 2019

A Probabilistic Approach to Floating-Point Arithmetic.

[BibT_eX]

[DOI]

Fredrik Dahlqvist

Rocco Salvia

Proceedings of the 53rd Asilomar Conference on Signals, Systems, and Computers, 2019

2018

KAPow: High-Accuracy, Low-Overhead Online Per-Module Power Estimation for FPGA Designs.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2018

Polyhedral-Based Dynamic Loop Pipelining for High-Level Synthesis.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Scheduling Weakly Consistent C Concurrency for Reconfigurable Hardware.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2018

An Application- and Platform-agnostic Runtime Management Framework for Multicore Systems.

[BibT_eX]

[DOI]

Bashir M. Al-Hashimi

Proceedings of the 8th International Joint Conference on Pervasive and Embedded Computing and Communication Systems, 2018

KOCL: Kernel-level Power Estimation for Arbitrary FPGA-SoC-accelerated OpenCL Applications.

[BibT_eX]

[DOI]

Georgios Chatzianastasiou

Proceedings of the International Workshop on OpenCL, 2018

An Efficient FPGA-based Axis-Aligned Box Tool for Embedded Computer Graphics.

[BibT_eX]

[DOI]

Proceedings of the 28th International Conference on Field Programmable Logic and Applications, 2018

Concurrency-Aware Thread Scheduling for High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 26th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2018

Hardware Compilation of Deep Neural Networks: An Overview.

[BibT_eX]

[DOI]

Proceedings of the 29th IEEE International Conference on Application-specific Systems, 2018

Digit Elision for Arbitrary-accuracy Iterative Computation.

[BibT_eX]

[DOI]

Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

A High Throughput Polynomial and Rational Function Approximations Evaluator.

[BibT_eX]

[DOI]

Nicolas Brisebarre

Proceedings of the 25th IEEE Symposium on Computer Arithmetic, 2018

2017

Certified Roundoff Error Bounds Using Semidefinite Programming.

[BibT_eX]

[DOI]

Victor Magron

Alastair F. Donaldson

ACM Trans. Math. Softw., 2017

Custom Multicache Architectures for Heap Manipulating Programs.

[BibT_eX]

[DOI]

Kermin Elliott Fleming

Hsin-Jung Yang

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2017

KOCL: Power Self- Awareness for Arbitrary FPGA-SoC-Accelerated OpenCL Applications.

[BibT_eX]

[DOI]

IEEE Des. Test, 2017

Automatic Software and Computing Hardware Co-design for Predictive Control.

[BibT_eX]

[DOI]

CoRR, 2017

Nonlinear Predictive Control on a Heterogeneous Computing Platform.

[BibT_eX]

[DOI]

CoRR, 2017

Automatically comparing memory consistency models.

[BibT_eX]

[DOI]

Mark Batty

Tyler Sorensen

Proceedings of the 44th ACM SIGPLAN Symposium on Principles of Programming Languages, 2017

Pass a pointer: Exploring shared virtual memory abstractions in OpenCL tools for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Technology, 2017

architect: Arbitrary-precision constant-hardware iterative compute.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Technology, 2017

Tile size selection for optimized memory reuse in high-level synthesis.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

STRIPE: Signal selection for runtime power estimation.

[BibT_eX]

[DOI]

Proceedings of the 27th International Conference on Field Programmable Logic and Applications, 2017

Hardware Synthesis of Weakly Consistent C Concurrency.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

FPGAs in the Cloud.

[BibT_eX]

[DOI]

Proceedings of the 2017 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2017

Quantifying error: Extending static timing analysis with probabilistic transitions.

[BibT_eX]

[DOI]

Kevin E. Murray

Vaughn Betz

George Anthony Constantinides

Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2017

Algorithms and Arithmetic: Choose Wisely.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Symposium on Computer Arithmetic, 2017

Run fast when you can: Loop pipelining with uncertain and non-uniform memory dependencies.

[BibT_eX]

[DOI]

Proceedings of the 51st Asilomar Conference on Signals, Systems, and Computers, 2017

2016

Separation Logic for High-Level Synthesis.

[BibT_eX]

[DOI]

Felix J. Winterstein

Samuel R. Bayliss

ACM Trans. Reconfigurable Technol. Syst., 2016

Balancing Locality and Concurrency: Solving Sparse Triangular Systems on GPUs.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE International Conference on High Performance Computing, 2016

An efficient implementation of online arithmetic.

[BibT_eX]

[DOI]

Proceedings of the 2016 International Conference on Field-Programmable Technology, 2016

A Case for Work-stealing on FPGAs with OpenCL Atomics.

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Automatically Optimizing the Latency, Area, and Accuracy of C Programs for High-Level Synthesis.

[BibT_eX]

[DOI]

Xitong Gao

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Knowledge is Power: Module-level Sensing for Runtime Optimisation (Abstact Only).

[BibT_eX]

[DOI]

Proceedings of the 2016 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2016

Loop Splitting for Efficient Pipelining in High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

KAPow: A System Identification Approach to Online Per-Module Power Estimation in FPGA Designs.

[BibT_eX]

[DOI]

Proceedings of the 24th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2016

Multi-objective Co-design for model predictive control with an FPGA.

[BibT_eX]

[DOI]

Proceedings of the 15th European Control Conference, 2016

What is different about embedded optimization?

[BibT_eX]

[DOI]

Proceedings of the 15th European Control Conference, 2016

2015

Imprecise Datapath Design: An Overclocking Approach.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2015

Communication Optimization of Iterative Sparse Matrix-Vector Multiply on GPUs and FPGAs.

[BibT_eX]

[DOI]

IEEE Trans. Parallel Distributed Syst., 2015

A Low Complexity Scaling Method for the Lanczos Kernel in Fixed-Point Arithmetic.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2015

Seeing Shapes in Clouds: On the Performance-Cost trade-off for Heterogeneous Infrastructure-as-a-Service.

[BibT_eX]

[DOI]

Gordon Inggs

CoRR, 2015

Custom-sized caches in application-specific memory hierarchies.

[BibT_eX]

[DOI]

Proceedings of the 2015 International Conference on Field Programmable Technology, 2015

PushPush: Seamless integration of hardware and software objects via function calls over AXI.

[BibT_eX]

[DOI]

Ivan Beretta

Dan R. Ghica

Proceedings of the 25th International Conference on Field Programmable Logic and Applications, 2015

MATCHUP: Memory Abstractions for Heap Manipulating Programs.

[BibT_eX]

[DOI]

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Delay-Bounded Routing for Shadow Registers.

[BibT_eX]

[DOI]

Eddie Hung

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Numerical Program Optimization for High-Level Synthesis.

[BibT_eX]

[DOI]

Xitong Gao

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

System-level Linking of Synthesised Hardware and Compiled Software Using a Higher-order Type System.

[BibT_eX]

[DOI]

Dan R. Ghica

Proceedings of the 2015 ACM/SIGDA International Symposium on Field-Programmable Gate Arrays, 2015

Offline Synthesis of Online Dependence Testing: Parametric Loop Pipelining for HLS.

[BibT_eX]

[DOI]

Proceedings of the 23rd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2015

Fast FPGA prototyping toolbox for embedded optimization.

[BibT_eX]

[DOI]

Proceedings of the 14th European Control Conference, 2015

Transparent linking of compiled software and synthesized hardware.

[BibT_eX]

[DOI]

Dan R. Ghica

Proceedings of the 2015 Design, Automation & Test in Europe Conference & Exhibition, 2015

Computer architectures to close the loop in real-time optimization.

[BibT_eX]

[DOI]

Andrea Picciau

Proceedings of the 54th IEEE Conference on Decision and Control, 2015

2014

Predictive Control Using an FPGA With Application to Aircraft Control.

[BibT_eX]

[DOI]

Edward Nicholas Hartley

IEEE Trans. Control. Syst. Technol., 2014

On the Systematic Creation of Faithfully Rounded Truncated Multipliers and Arrays.

[BibT_eX]

[DOI]

Theo A. Drane

Thomas M. Rose

IEEE Trans. Computers, 2014

Embedded Online Optimization for Model Predictive Control at Megahertz Rates.

[BibT_eX]

[DOI]

Paul J. Goulart

Stefan Richter

Manfred Morari

IEEE Trans. Autom. Control., 2014

Mitigation of process variation effect in FPGAs with partial rerouting method.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

Classification on variation maps: a new placement strategy to alleviate process variation on FPGA.

[BibT_eX]

[DOI]

IEICE Electron. Express, 2014

Constrained LQR for low-precision data representation.

[BibT_eX]

[DOI]

Autom., 2014

Efficient FPGA implementation of digit parallel online arithmetic operators.

[BibT_eX]

[DOI]

Proceedings of the 2014 International Conference on Field-Programmable Technology, 2014

FPGA implementation of an interior point method for high-speed model predictive control.

[BibT_eX]

[DOI]

Helfried Peyrl

Andreas Burg

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Area implications of memory partitioning for high-level synthesis on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 24th International Conference on Field Programmable Logic and Applications, 2014

Separation Logic-Assisted Code Transformations for Efficient High-Level Synthesis.

[BibT_eX]

[DOI]

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Compiling Higher Order Functional Programs to Composable Digital Hardware.

[BibT_eX]

[DOI]

Eduardo Aguilar-Pelaez

Proceedings of the 22nd IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2014

Datapath Synthesis for Overclocking: Online Arithmetic for Latency-Accuracy Trade-offs.

[BibT_eX]

[DOI]

Proceedings of the 51st Annual Design Automation Conference 2014, 2014

GPU vs FPGA: A Comparative Analysis for Non-standard Precision.

[BibT_eX]

[DOI]

Umar Ibrahim Minhas

Proceedings of the Reconfigurable Computing: Architectures, Tools, and Applications, 2014

2013

A Scalable Precision Analysis Framework.

[BibT_eX]

[DOI]

IEEE Trans. Multim., 2013

Control-Theoretic Forward Error Analysis of Iterative Numerical Algorithms.

[BibT_eX]

[DOI]

Ammar Hasan

IEEE Trans. Autom. Control., 2013

Overclocking datapath for latency-error tradeoff.

[BibT_eX]

[DOI]

Proceedings of the 2013 IEEE International Symposium on Circuits and Systems (ISCAS2013), 2013

High-level synthesis of dynamic data structures: A case study using Vivado HLS.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Exploiting stochastic delay variability on FPGAs with adaptive partial rerouting.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

SOAP: Structural optimization of arithmetic expressions for high-level synthesis.

[BibT_eX]

[DOI]

Xitong Gao

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

Revisiting the reduction circuit: A case study for simultaneous architecture and precision optimisation.

[BibT_eX]

[DOI]

Proceedings of the 2013 International Conference on Field-Programmable Technology, 2013

FPGA-based K-means clustering using tree-based data structures.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

SMI: Slack Measurement Insertion for online timing monitoring in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

A variation-adaptive retiming method exploiting reconfigurability.

[BibT_eX]

[DOI]

Proceedings of the 23rd International Conference on Field programmable Logic and Applications, 2013

Word-length optimization beyond straight line code.

[BibT_eX]

[DOI]

Proceedings of the 2013 ACM/SIGDA International Symposium on Field Programmable Gate Arrays, 2013

Accuracy-Performance Tradeoffs on an FPGA through Overclocking.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Application Composition and Communication Optimization in Iterative Solvers Using FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 21st IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2013

Energy-aware MPC co-design for DC-DC converters.

[BibT_eX]

[DOI]

Proceedings of the 12th European Control Conference, 2013

A predictive control solver for low-precision data representation.

[BibT_eX]

[DOI]

Proceedings of the 12th European Control Conference, 2013

Embedded Predictive Control on an FPGA using the Fast Gradient Method.

[BibT_eX]

[DOI]

Paul J. Goulart

Stefan Richter

Manfred Morari

Proceedings of the 12th European Control Conference, 2013

2012

Automated Mapping of the MapReduce Pattern onto Parallel Computing Platforms.

[BibT_eX]

[DOI]

J. Signal Process. Syst., 2012

Optimizing Hardware Design by Composing Utility-Directed Transformations.

[BibT_eX]

[DOI]

IEEE Trans. Computers, 2012

A Stable and Efficient Method for Solving a Convex Quadratic Program with Application to Optimal Control.

[BibT_eX]

[DOI]

SIAM J. Optim., 2012

Analytical synthesis of bandwidth-efficient SDRAM address generators.

[BibT_eX]

[DOI]

Microprocess. Microsystems, 2012

A sparse and condensed QP formulation for predictive control of LTI systems.

[BibT_eX]

[DOI]

Autom., 2012

Correctly rounded constant integer division via multiply-add.

[BibT_eX]

[DOI]

Wai-chuen Cheung

Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

Enhancing performance of Tall-Skinny QR factorization using FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A two-stage variation-aware placement method for FPGAS exploiting variation maps classification.

[BibT_eX]

[DOI]

Proceedings of the 22nd International Conference on Field Programmable Logic and Applications (FPL), 2012

A scalable approach for automated precision analysis.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Optimizing SDRAM bandwidth for custom FPGA loop accelerators.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 20th International Symposium on Field Programmable Gate Arrays, 2012

Online Measurement of Timing in Circuits: For Health Monitoring and Dynamic Voltage & Frequency Scaling.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Fixed Point Lanczos: Sustaining TFLOP-equivalent Performance in FPGAs for Scientific Computing.

[BibT_eX]

[DOI]

Proceedings of the 2012 IEEE 20th Annual International Symposium on Field-Programmable Custom Computing Machines, 2012

Resource-Efficient Designs Using an Aspect-Oriented Approach.

[BibT_eX]

[DOI]

José Gabriel F. Coutinho

Sujit Bhattacharya

Proceedings of the 15th IEEE International Conference on Computational Science and Engineering, 2012

Towards a fixed point QP solver for predictive control.

[BibT_eX]

[DOI]

Proceedings of the 51th IEEE Conference on Decision and Control, 2012

FPGA Paranoia: Testing Numerical Properties of FPGA Floating Point IP-Cores.

[BibT_eX]

[DOI]

Xuan You Tan

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

A High Throughput FPGA-Based Implementation of the Lanczos Method for the Symmetric Extremal Eigenvalue Problem.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2012

2011

Optimizing memory bandwidth use and performance for matrix-vector multiplication in iterative methods.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2011

Bounding Variable Values and Round-Off Effects Using Handelman Representations.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2011

Guest Editors' Introduction: Surveying the Landscape of FPGA Accelerator Research.

[BibT_eX]

[DOI]

Nicola Nicolici

IEEE Des. Test Comput., 2011

Numerical Data Representations for FPGA-Based Scientific Computing.

[BibT_eX]

[DOI]

Adam B. Kinsman

Nicola Nicolici

IEEE Des. Test Comput., 2011

Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organization.

[BibT_eX]

[DOI]

Comput. J., 2011

An efficient algorithm for the solution of a coupled Sylvester equation appearing in descriptor systems.

[BibT_eX]

[DOI]

Bryn Ll. Jones

Autom., 2011

A parallel formulation for predictive control with nonuniform hold constraints.

[BibT_eX]

[DOI]

Keck Voon Ling

Annu. Rev. Control., 2011

Health monitoring of live circuits in FPGAs based on time delay measurement (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

An FPGA implementation of a sparse quadratic programming solver for constrained predictive control.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 19th International Symposium on Field Programmable Gate Arrays, 2011

Optimisation of mutually exclusive arithmetic sum-of-products.

[BibT_eX]

[DOI]

Proceedings of the Design, Automation and Test in Europe, 2011

Parallel move blocking Model Predictive Control.

[BibT_eX]

[DOI]

Keck Voon Ling

Proceedings of the 50th IEEE Conference on Decision and Control and European Control Conference, 2011

A condensed and sparse QP formulation for predictive control.

[BibT_eX]

[DOI]

Proceedings of the 50th IEEE Conference on Decision and Control and European Control Conference, 2011

Solving a positive definite system of linear equations via the matrix exponential.

[BibT_eX]

[DOI]

Ammar Hasan

Proceedings of the 50th IEEE Conference on Decision and Control and European Control Conference, 2011

Accurate Floating Point Arithmetic through Hardware Error-Free Transformations.

[BibT_eX]

[DOI]

Manouk V. Manoukian

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

The Krawczyk Algorithm: Rigorous Bounds for Linear Equation Solution on an FPGA.

[BibT_eX]

[DOI]

Christophe Le Lann

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

Application Specific Memory Access, Reuse and Reordering for SDRAM.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, Tools and Applications, 2011

2010

An Automated Flow for Arithmetic Component Generation in Field-Programmable Gate Arrays.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2010

An Optimized Hardware Architecture of a Multivariate Gaussian Random Number Generator.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2010

A High Throughput FPGA-Based Floating Point Conjugate Gradient Implementation for Dense Matrices.

[BibT_eX]

[DOI]

ACM Trans. Reconfigurable Technol. Syst., 2010

Efficient Heterogeneous Architecture Floorplan Optimization using Analytical Methods.

[BibT_eX]

[DOI]

Asma Kahoul

ACM Trans. Reconfigurable Technol. Syst., 2010

FPGA Architecture Optimization Using Geometric Programming.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2010

FPGA implementation of an interior point solver for linear model predictive control.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field-Programmable Technology, 2010

Mapping Multiple Multivariate Gaussian Random Number Generators on an FPGA.

[BibT_eX]

[DOI]

Proceedings of the International Conference on Field Programmable Logic and Applications, 2010

A Scripting Engine for Combining Design Transformations.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Automated Precision Analysis: A Polynomial Algebraic Approach.

[BibT_eX]

[DOI]

Proceedings of the 18th IEEE Annual International Symposium on Field-Programmable Custom Computing Machines, 2010

Customizable Composition and Parameterization of Hardware Design Transformations.

[BibT_eX]

[DOI]

Proceedings of the 13th Euromicro Conference on Digital System Design, 2010

A fast well-conditioned interior point method for predictive control.

[BibT_eX]

[DOI]

Proceedings of the 49th IEEE Conference on Decision and Control, 2010

An ISS and l-stability approach to forward error analysis of iterative numerical algorithms.

[BibT_eX]

[DOI]

Ammar Hasan

Proceedings of the 49th IEEE Conference on Decision and Control, 2010

Design of a Financial Application Driven Multivariate Gaussian Random Number Generator for an FPGA.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2010

A Fused Hybrid Floating-Point and Fixed-Point Dot-Product for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2010

Optimising Memory Bandwidth Use for Matrix-Vector Multiplication in Iterative Methods.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2010

Preconditioners for inexact interior point methods for predictive control.

[BibT_eX]

[DOI]

Proceedings of the American Control Conference, 2010

2009

A Floating-point Extended Kalman Filter Implementation for Autonomous Mobile Robots.

[BibT_eX]

[DOI]

Vanderlei Bonato

Eduardo Marques

J. Signal Process. Syst., 2009

Synthesis and Optimization of 2D Filter Designs for Heterogeneous FPGAs.

[BibT_eX]

[DOI]

Sung-Boem Park

ACM Trans. Reconfigurable Technol. Syst., 2009

Robust Real-Time Super-Resolution on FPGA and an Application to Video Enhancement.

[BibT_eX]

[DOI]

Maria E. Angelopoulou

ACM Trans. Reconfigurable Technol. Syst., 2009

Word-length selection for power minimization via nonlinear optimization.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2009

Combining Data Reuse With Data-Level Parallelization for FPGA-Targeted Hardware Compilation: A Geometric Programming Framework.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2009

Data-reuse exploration under an on-chip memory constraint for low-power FPGA-based systems.

[BibT_eX]

[DOI]

IET Comput. Digit. Tech., 2009

Concurrently optimizing FPGA architecture parameters and transistor sizing: Implications for FPGA design.

[BibT_eX]

[DOI]

Steven J. E. Wilton

Proceedings of the 2009 International Conference on Field-Programmable Technology, 2009

Area estimation and optimisation of FPGA routing fabrics.

[BibT_eX]

[DOI]

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

Optimising designs by combining model-based and pattern-based transformations.

[BibT_eX]

[DOI]

José Gabriel de Figueiredo Coutinho

Proceedings of the 19th International Conference on Field Programmable Logic and Applications, 2009

More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control.

[BibT_eX]

[DOI]

Proceedings of the FCCM 2009, 2009

Tutorial paper: Parallel architectures for model predictive control.

[BibT_eX]

[DOI]

Proceedings of the 10th European Control Conference, 2009

Word-Length Optimization and Error Analysis of a Multivariate Gaussian Random Number Generator.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2009

Heterogeneous Architecture Exploration: Analysis vs. Parameter Sweep.

[BibT_eX]

[DOI]

Asma Kahoul

Proceedings of the Reconfigurable Computing: Architectures, 2009

2008

Guest Editorial: Field Programmable Technology.

[BibT_eX]

[DOI]

Wai-Kei Mak

Theerayod Wiangtong

J. Signal Process. Syst., 2008

Integrated Floorplanning, Module-Selection, and Architecture Generationfor Reconfigurable Devices.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2008

A Parallel Hardware Architecture for Scale and Rotation Invariant Feature Detection.

[BibT_eX]

[DOI]

Vanderlei Bonato

Eduardo Marques

IEEE Trans. Circuits Syst. Video Technol., 2008

Custom parallel caching schemes for hardware-accelerated image compression.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2008

Glitch-aware output switching activity from word-level statistics.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2008), 2008

Co-optimisation of datapath and memory in outer loop pipelining.

[BibT_eX]

[DOI]

Kieron Turkington

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

A floating-point solver for band structured linear equations.

[BibT_eX]

[DOI]

Proceedings of the 2008 International Conference on Field-Programmable Technology, 2008

Combining data reuse exploitationwith data-level parallelization for FPGA targeted hardware compilation: A geometric programming framework.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

An FPGA-based implementation of the MINRES algorithm.

[BibT_eX]

[DOI]

Proceedings of the FPL 2008, 2008

Compiling C-like Languages to FPGA Hardware: Some Novel Approaches Targeting Data Memory Organisation.

[BibT_eX]

[DOI]

Proceedings of the Visions of Computer Science, 2008

Multivariate Gaussian Random Number Generator Targeting Specific Resource Utilization in an FPGA.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2008

A High Throughput FPGA-based Floating Point Conjugate Gradient Implementation.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures, 2008

A Parallel Hardware Architecture for Image Feature Detection.

[BibT_eX]

[DOI]

Vanderlei Bonato

Eduardo Marques

Proceedings of the Reconfigurable Computing: Architectures, 2008

FPGA-based Real-time Super-Resolution on an Adaptive Image Sensor.

[BibT_eX]

[DOI]

Maria E. Angelopoulou

Proceedings of the Reconfigurable Computing: Architectures, 2008

2007

Run-Time Integration of Reconfigurable Video Processing Systems.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2007

Special issue on Field-Programmable Technology.

[BibT_eX]

[DOI]

J. Real Time Image Process., 2007

ROM to DSP block transfer for resource constrained synthesis.

[BibT_eX]

[DOI]

Gareth W. Morris

IET Comput. Digit. Tech., 2007

CCDF and Monte Carlo Analysis of a Digital Polar Transmitter for Ultra-Wideband System.

[BibT_eX]

[DOI]

Kwang-Hwee Seah

Michael Yan Wah Chia

Christos Papavassiliou

Proceedings of the IEEE 18th International Symposium on Personal, 2007

Fused-Arithmetic Unit Generation for Reconfigurable Devices using Common Subgraph Extraction.

[BibT_eX]

[DOI]

Proceedings of the 2007 International Conference on Field-Programmable Technology, 2007

On the feasibility of early routing capacitance estimation for FPGAs.

[BibT_eX]

[DOI]

Proceedings of the FPL 2007, 2007

Automatic On-chip Memory Minimization for Data Reuse.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

A Hybrid Memory Sub-system for Video Coding Applications.

[BibT_eX]

[DOI]

Proceedings of the IEEE Symposium on Field-Programmable Custom Computing Machines, 2007

2006

Word-length optimization for differentiable nonlinear systems.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2006

Optimal combined word-length allocation and architectural synthesis of digital signal processing circuits.

[BibT_eX]

[DOI]

Gabriel Caffarena

Carlos Carreras

Octavio Nieto-Taladriz

IEEE Trans. Circuits Syst. II Express Briefs, 2006

Accuracy-Guaranteed Bit-Width Optimization.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2006

On-Chip Communication in Run-Time Assembled Reconfigurable Systems.

[BibT_eX]

[DOI]

Proceedings of 2006 International Conference on Embedded Computer Systems: Architectures, 2006

Fast word-level power models for synthesis of FPGA-based arithmetic.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2006), 2006

Modeling of glitch effects in FPGA based arithmetic circuits.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

PowerBit - power aware arithmetic bit-width optimization.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

An FPGA implementation of the simplex algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

The cost of data dependence in motion vector estimation for reconfigurable platforms.

[BibT_eX]

[DOI]

Proceedings of the 2006 IEEE International Conference on Field Programmable Technology, 2006

FPGA Based Acceleration of the Linpack Benchmark: A High Level Code Transformation Approach.

[BibT_eX]

[DOI]

Kieron Turkington

Philip Heng Wai Leong

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

A Novel Heuristic and Provable Bounds for Reconfigurable Architecture Design.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Data Reuse Exploration for FPGA Based Platforms Applied to the Full Search Motion Estimation Algorithm.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

High-Level Power Optimization for Digital Signal Processing in Reconfigurable Logic.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Reconfiguration and Fine-Grained Redundancy for Fault Tolerance in FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Dynamic Memory Sub-System for Reconfigurable Platforms.

[BibT_eX]

[DOI]

Proceedings of the 2006 International Conference on Field Programmable Logic and Applications (FPL), 2006

Yield enhancements of design-specific FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 14th International Symposium on Field Programmable Gate Arrays, 2006

A Novel Hueristic and Provable Bounds for Reconfigurable Architecture Design.

[BibT_eX]

[DOI]

Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006

A Flexible Multi-port Caching Scheme for Reconfigurable Platforms.

[BibT_eX]

[DOI]

Proceedings of the Reconfigurable Computing: Architectures and Applications, 2006

2005

Optimum and heuristic synthesis of multiple word-length architectures.

[BibT_eX]

[DOI]

IEEE Trans. Very Large Scale Integr. Syst., 2005

A heuristic approach for multiple restricted multiplication.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

A novel 2D filter design methodology.

[BibT_eX]

[DOI]

Proceedings of the International Symposium on Circuits and Systems (ISCAS 2005), 2005

An Analytical Approach to Generation and Exploration of Reconfigurable Architectures.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Power and Area Optimization for Multiple Restricted Multiplication.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

FPGA-Accelerated Reconstruction of Gene Regulatory Networks.

[BibT_eX]

[DOI]

Iosifina Pournara

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow.

[BibT_eX]

[DOI]

Gareth W. Morris

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic.

[BibT_eX]

[DOI]

Chun Te Ewe

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Parameterized Logic Power Consumption Models for FPGA based Systems.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Heterogeneity Exploration for Multiple 2D Filter Designs.

[BibT_eX]

[DOI]

Proceedings of the 2005 International Conference on Field Programmable Logic and Applications (FPL), 2005

Exploration of heterogeneous reconfigurable architectures (abstract only).

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

Analysis of yield loss due to random photolithographic defects in the interconnect structure of FPGAs.

[BibT_eX]

[DOI]

Proceedings of the ACM/SIGDA 13th International Symposium on Field Programmable Gate Arrays, 2005

A Novel 2D Filter Design Methodology for Heterogeneous Devices.

[BibT_eX]

[DOI]

Proceedings of the 13th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2005), 2005

2004

Guest Editors' Introduction: Field Programmable Logic and Applications.

[BibT_eX]

[DOI]

José T. de Sousa

IEEE Trans. Computers, 2004

Multiple Restricted Multiplication.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

A Structured Methodology for System-on-an-FPGA Design.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 2004

Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation.

[BibT_eX]

[DOI]

Chun Te Ewe

Proceedings of the Field Programmable Logic and Application, 2004

A Structured System Methodology for FPGA Based System-on-A-Chip Design.

[BibT_eX]

[DOI]

Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Migrating Functionality from ROMS to Embedded Multipliers.

[BibT_eX]

[DOI]

Gareth W. Morris

Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Word-Length Optimization of Folded Polynomial Evaluation.

[BibT_eX]

[DOI]

Abunaser Miah

Proceedings of the 12th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2004), 2004

Synthesis and optimization of DSP algorithms.

[BibT_eX]

Kluwer, ISBN: 978-1-4020-7930-6, 2004

2003

Synthesis of saturation arithmetic architectures.

[BibT_eX]

[DOI]

ACM Trans. Design Autom. Electr. Syst., 2003

Wordlength optimization for linear digital signal processing.

[BibT_eX]

[DOI]

IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2003

Review of Computer arithmetic algorithms by Israel Koren. A.K. Peters.

[BibT_eX]

[DOI]

SIGACT News, 2003

Architectures for function evaluation on FPGAs.

[BibT_eX]

[DOI]

Proceedings of the 2003 International Symposium on Circuits and Systems, 2003

A Reconfigurable Platform for Real-Time Embedded Video Image Processing.

[BibT_eX]

[DOI]

Proceedings of the Field Programmable Logic and Application, 13th International Conference, 2003

Perturbation Analysis for Word-length Optimization.

[BibT_eX]

[DOI]

Proceedings of the 11th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2003), 2003

2002

The complexity of multiple wordlength assignment.

[BibT_eX]

[DOI]

Gerhard J. Woeginger

Appl. Math. Lett., 2002

Strassen's matrix multiplication for customisable processors.

[BibT_eX]

[DOI]

Henry M. D. Ip

James D. Low

Shay Ping Seng

Paul Metzgen

Proceedings of the 2002 IEEE International Conference on Field-Programmable Technology, 2002

Optimum Wordlength Allocation.

[BibT_eX]

[DOI]

Proceedings of the 10th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2002), 2002

2001

The Multiple Wordlength Paradigm.

[BibT_eX]

[DOI]

Proceedings of the 9th Annual IEEE Symposium on Field-Programmable Custom Computing Machines, 2001

Heuristic datapath allocation for multiple wordlength systems.

[BibT_eX]

[DOI]

Proceedings of the Conference on Design, Automation and Test in Europe, 2001

2000

Active filter synthesis based on tuneable log-domain lossy integrators.

[BibT_eX]

[DOI]

Nikos Fragoulis

Ioannis Haritantis

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Roundoff-noise shaping in filter design.

[BibT_eX]

[DOI]

Proceedings of the IEEE International Symposium on Circuits and Systems, 2000

Multiple-Wordlength Resource Binding.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 2000

Multiple Precision for Resource Minimization.

[BibT_eX]

[DOI]

Proceedings of the 8th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2000), 2000

1999

<i>Synthia</i>: Synthesis of Interacting Automata Targeting LUT-based FPGAs.

[BibT_eX]

[DOI]

Proceedings of the Field-Programmable Logic and Applications, 9th International Workshop, 1999

1991

Layered DCT video coding for embedded data transmission over BISDN.

[BibT_eX]

[DOI]

D. K. Mitrakos

Proceedings of the 1991 International Conference on Acoustics, 1991

1983

Maximum likelihood estimation of composite source models for image coding.

[BibT_eX]

[DOI]

D. K. Mitrakos

Proceedings of the IEEE International Conference on Acoustics, 1983

1982

Composite source coding techniques for image bandwidth compression.

[BibT_eX]

[DOI]

D. K. Mitrakos