Georg Weissenbacher

Orcid: 0000-0002-0143-632X

Affiliations:
  • TU Vienna, Institute of Logic and Computation, Austria
  • Princeton University, Department of Electrical Engineering, NJ, USA
  • ETH Zurich, Computer Systems Institute, Switzerland
  • Oxford University, UK (PhD 2010)


According to our database1, Georg Weissenbacher authored at least 57 papers between 2005 and 2024.

Collaborative distances:
  • Dijkstra number2 of four.
  • Erdős number3 of four.

Timeline

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Bibliography

2024
Finding ∀∃ Hyperbugs using Symbolic Execution.
Proc. ACM Program. Lang., 2024

Differential Property Monitoring for Backdoor Detection.
Proceedings of the Formal Methods and Software Engineering, 2024

Statistical Profiling of Micro-Architectural Traces and Machine Learning for Spectre Detection: A Systematic Evaluation.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2024

Verifying Global Two-Safety Properties in Neural Networks with Confidence.
Proceedings of the Computer Aided Verification - 36th International Conference, 2024

2023
A Formalization of Heisenbugs and Their Causes.
Proceedings of the Software Engineering and Formal Methods - 21st International Conference, 2023

2021
Mutation testing with hyperproperties.
Softw. Syst. Model., 2021

Preface of the special issue on the Conference on Formal Methods in Computer-Aided Design 2017.
Formal Methods Syst. Des., 2021

Rely-guarantee bound analysis of parameterized concurrent shared-memory programs.
Formal Methods Syst. Des., 2021

Preface of the special issue on the conference on computer-aided verification 2018.
Formal Methods Syst. Des., 2021

Bounded Model Checking of Speculative Non-Interference.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

Model Checking AUTOSAR Components with CBMC.
Proceedings of the Formal Methods in Computer Aided Design, 2021

2020
Extracting safe thread schedules from incomplete model checking results.
Int. J. Softw. Tools Technol. Transf., 2020

Language Inclusion for Finite Prime Event Structures.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2020

Multi-linear Strategy Extraction for QBF Expansion Proofs via Local Soundness.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2020, 2020

RAT Elimination.
Proceedings of the LPAR 2020: 23rd International Conference on Logic for Programming, 2020

Thread-modular Counter Abstraction for Parameterized Program Safety.
Proceedings of the 2020 Formal Methods in Computer Aided Design, 2020

2019
Model-based, Mutation-driven Test-case Generation Via Heuristic-guided Branching Search.
ACM Trans. Embed. Comput. Syst., 2019

Model-Based Diagnosis with Multiple Observations.
Proceedings of the Twenty-Eighth International Joint Conference on Artificial Intelligence, 2019

2018
Randomized testing of distributed systems with probabilistic guarantees.
Proc. ACM Program. Lang., 2018

Rely-Guarantee Reasoning for Automated Bound Analysis of Lock-Free Algorithms.
Proceedings of the 2018 Formal Methods in Computer Aided Design, 2018

A Separation Logic with Data: Small Models and Automation.
Proceedings of the Automated Reasoning - 9th International Joint Conference, 2018

2017
Preface of the Special Issue in Memoriam Helmut Veith.
Formal Methods Syst. Des., 2017

Dynamic Reductions for Model Checking Concurrent Software.
Proceedings of the Verification, Model Checking, and Abstract Interpretation, 2017

2016
Labelled Interpolation Systems for Hyper-Resolution, Clausal, and Local Proofs.
J. Autom. Reason., 2016

Abstraction and mining of traces to explain concurrency bugs.
Formal Methods Syst. Des., 2016

Vienna Verification Tool: IC3 for Parallel Software - (Competition Contribution).
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2016

Error Invariants for Concurrent Traces.
Proceedings of the FM 2016: Formal Methods, 2016

2015
Boolean Satisfiability Solvers and Their Applications in Model Checking.
Proc. IEEE, 2015

Under-approximating loops in C programs for fast counterexample detection.
Formal Methods Syst. Des., 2015

The FMCAD 2015 Graduate Student Forum.
Proceedings of the Formal Methods in Computer-Aided Design, 2015

Proving Safety with Trace Automata and Bounded Model Checking.
Proceedings of the FM 2015: Formal Methods, 2015

2014
Boolean Satisfiability: Solvers and Extensions.
Proceedings of the Software Systems Safety, 2014

Incremental bounded software model checking.
Proceedings of the 2014 International Symposium on Model Checking of Software, 2014

Silicon fault diagnosis using sequence interpolation with backbones.
Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, 2014

Reduction of Resolution Refutations and Interpolants via Subsumption.
Proceedings of the Hardware and Software: Verification and Testing, 2014

Counterexample to Induction-Guided Abstraction-Refinement (CTIGAR).
Proceedings of the Computer Aided Verification - 26th International Conference, 2014

2013
Advanced SAT Techniques for Abstract Argumentation.
Proceedings of the Computational Logic in Multi-Agent Systems, 2013

2012
Boolean Satisfiability Solvers: Techniques and Extensions.
Proceedings of the Software Safety and Security - Tools for Analysis and Verification, 2012

Wolverine: Battling Bugs with Interpolants - (Competition Contribution).
Proceedings of the Tools and Algorithms for the Construction and Analysis of Systems, 2012

Interpolant Strength Revisited.
Proceedings of the Theory and Applications of Satisfiability Testing - SAT 2012, 2012

Coverage-Based Trace Signal Selection for Fault Localisation in Post-silicon Validation.
Proceedings of the Hardware and Software: Verification and Testing, 2012

Parallel Assertions for Architectures with Weak Memory Models.
Proceedings of the Automated Technology for Verification and Analysis, 2012

2011
SAT-based techniques for determining backbones for post-silicon fault localisation.
Proceedings of the 2011 IEEE International High Level Design Validation and Test Workshop, 2011

Post-silicon fault localisation using maximum satisfiability and backbones.
Proceedings of the International Conference on Formal Methods in Computer-Aided Design, 2011

Interpolation-Based Software Verification with Wolverine.
Proceedings of the Computer Aided Verification - 23rd International Conference, 2011

2010
Program analysis with interpolants.
PhD thesis, 2010

Verification and falsification of programs with loops using predicate abstraction.
Formal Aspects Comput., 2010

Interpolant Strength.
Proceedings of the Verification, 2010

2009
An Interpolating Decision Procedure for Transitive Relations with Uninterpreted Functions.
Proceedings of the Hardware and Software: Verification and Testing, 2009

Mutation-Based Test Case Generation for Simulink Models.
Proceedings of the Formal Methods for Components and Objects - 8th International Symposium, 2009

2008
A Survey of Automated Techniques for Formal Software Verification.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2008

2007
SAT-Based Summarization for Boolean Programs.
Proceedings of the Model Checking Software, 2007

Model checking concurrent linux device drivers.
Proceedings of the 22nd IEEE/ACM International Conference on Automated Software Engineering (ASE 2007), 2007

A Complete Bounded Model Checking Algorithm for Pushdown Systems.
Proceedings of the Hardware and Software: Verification and Testing, 2007

Lifting Propositional Interpolants to the Word-Level.
Proceedings of the Formal Methods in Computer-Aided Design, 7th International Conference, 2007

2006
Counterexamples with Loops for Predicate Abstraction.
Proceedings of the Computer Aided Verification, 18th International Conference, 2006

2005
A Pattern for Formal Verification of Properties of Large Systems.
Proceedings of the EuroPLoP' 2005, 2005


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