Georg Ellguth

According to our database1, Georg Ellguth authored at least 28 papers between 2009 and 2024.

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Bibliography

2024
EdgeVision SoC: PPA-Impact of RTL-level Modifications.
Proceedings of the 37th IEEE International System-on-Chip Conference, 2024

2022
A 16-Channel Fully Configurable Neural SoC With 1.52 $\mu$W/Ch Signal Acquisition, 2.79 $\mu$W/Ch Real-Time Spike Classifier, and 1.79 TOPS/W Deep Neural Network Accelerator in 22 nm FDSOI.
IEEE Trans. Biomed. Circuits Syst., 2022

2021
Hardware Implementation of an OPC UA Server for Industrial Field Devices.
IEEE Trans. Very Large Scale Integr. Syst., 2021

The SpiNNaker 2 Processing Element Architecture for Hybrid Digital Neuromorphic Computing.
CoRR, 2021

2019
Dynamic Power Management for Neuromorphic Many-Core Systems.
IEEE Trans. Circuits Syst. I Regul. Pap., 2019

Performance Analysis of a Comparator Based Mixed-Signal Control Loop in 28 nm CMOS.
Proceedings of the 27th IFIP/IEEE International Conference on Very Large Scale Integration, 2019

2017

Live demonstration: Dynamic voltage and frequency scaling for neuromorphic many-core systems.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017


2016
A Biological-Realtime Neuromorphic System in 28 nm CMOS Using Low-Leakage Switched Capacitor Circuits.
IEEE Trans. Biomed. Circuits Syst., 2016

A database accelerator for energy-efficient query processing and optimization.
Proceedings of the IEEE Nordic Circuits and Systems Conference, 2016


2015
An Energy Efficient Multi-Gbit/s NoC Transceiver Architecture With Combined AC/DC Drivers and Stoppable Clocking in 65 nm and 28 nm CMOS.
IEEE J. Solid State Circuits, 2015

2014
A 12-b 4-MS/s SAR ADC With Configurable Redundancy in 28-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2014

Switched-Capacitor Realization of Presynaptic Short-Term-Plasticity and Stop-Learning Synapses in 28 nm CMOS.
CoRR, 2014

10.7 A 105GOPS 36mm<sup>2</sup> heterogeneous SDR MPSoC with energy-aware dynamic scheduling and iterative detection-decoding for 4G in 65nm CMOS.
Proceedings of the 2014 IEEE International Conference on Solid-State Circuits Conference, 2014

A compact on-chip IR-drop measurement system in 28 nm CMOS technology.
Proceedings of the IEEE International Symposium on Circuits and Systemss, 2014

2013
A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology.
IEEE Trans. Very Large Scale Integr. Syst., 2013

A Fast-Locking ADPLL With Instantaneous Restart Capability in 28-nm CMOS Technology.
IEEE Trans. Circuits Syst. II Express Briefs, 2013

2012
A 32 GBit/s communication SoC for a waferscale neuromorphic system.
Integr., 2012

On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links.
Int. J. Embed. Real Time Commun. Syst., 2012

A 335Mb/s 3.9mm<sup>2</sup> 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS.
Proceedings of the 2012 IEEE International Solid-State Circuits Conference, 2012

A power management architecture for fast per-core DVFS in heterogeneous MPSoCs.
Proceedings of the 2012 IEEE International Symposium on Circuits and Systems, 2012

2011
Mismatch characterization of high-speed NoC links using asynchronous sub-sampling.
Proceedings of the 2011 International Symposium on System on Chip, 2011

2010
A low-power cell-based-design multi-port register file in 65nm CMOS technology.
Proceedings of the International Symposium on Circuits and Systems (ISCAS 2010), May 30, 2010

Low power design of the X-GOLD<sup>®</sup> SDR 20 baseband processor.
Proceedings of the Design, Automation and Test in Europe, 2010

2009
Current conveyor based amplifier and adaptive buffer for use in an analog frontend.
Proceedings of the 16th IEEE International Conference on Electronics, 2009


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