Geordie Braceras

According to our database, Geordie Braceras authored at least 5 papers between 2007 and 2012.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of five.

2012

A 64 Mb SRAM in 32 nm High-k Metal-Gate SOI Technology With 0.7 V Operation Enabled by Stability, Write-Ability and Read-Ability Enhancements.

Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Carl Radens, Adnan Seferagic

IEEE J. Solid State Circuits, 2012

2011

A 64Mb SRAM in 32nm High-k metal-gate SOI technology with 0.7V operation enabled by stability, write-ability and read-ability enhancements.

Harold Pilo, Igor Arsovski, Kevin Batson, Geordie Braceras, John A. Gabric, Robert M. Houle, Steve Lamphier, Frank Pavlik, Adnan Seferagic, Liang-Yu Chen, Shang-Bin Ko, Carl Radens

Proceedings of the IEEE International Solid-State Circuits Conference, 2011

2009

An 8 Mb SRAM in 45 nm SOI Featuring a Two-Stage Sensing Scheme and Dynamic Power Management.

Vinod Ramadurai, Harold Pilo, John Andersen, Geordie Braceras, John A. Gabric, Daniel Geise, Steve Lamphier, Yue Tan

IEEE J. Solid State Circuits, 2009

2008

A 450ps Access-Time SRAM Macro in 45nm SOI Featuring a Two-Stage Sensing-Scheme and Dynamic Power Management.

Harold Pilo, Vaidyanathan Ramadurai, Geordie Braceras, John A. Gabric, Steve Lamphier, Yue Tan

Proceedings of the 2008 IEEE International Solid-State Circuits Conference, 2008

2007

An SRAM Design in 65-nm Technology Node Featuring Read and Write-Assist Circuits to Expand Operating Voltage.

Harold Pilo, Charlie Barwin, Geordie Braceras, Chris Browning, Steve Lamphier, Fred Towler

IEEE J. Solid State Circuits, 2007