Geoffrey W. Burr
Orcid: 0000-0001-5717-2549
According to our database1,
Geoffrey W. Burr
authored at least 34 papers
between 1998 and 2023.
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Bibliography
2023
A Heterogeneous and Programmable Compute-In-Memory Accelerator Architecture for Analog-AI Using Dense 2-D Mesh.
IEEE Trans. Very Large Scale Integr. Syst., 2023
Nat., 2023
Hardware-aware training for large-scale and diverse deep learning inference workloads using in-memory computing-based accelerators.
CoRR, 2023
Proceedings of the 2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits), 2023
Architectures and Circuits for Analog-memory-based Hardware Accelerators for Deep Neural Networks (Invited).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2023
Impact of Phase-Change Memory Drift on Energy Efficiency and Accuracy of Analog Compute-in-Memory Deep Learning Inference (Invited).
Proceedings of the IEEE International Reliability Physics Symposium, 2023
2022
IEEE Des. Test, 2022
Analog-memory-based 14nm Hardware Accelerator for Dense Deep Neural Networks including Transformers.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2022
2021
Toward Software-Equivalent Accuracy on Transformer-Based Deep Neural Networks With Analog Memory Devices.
Frontiers Comput. Neurosci., 2021
Circuit Techniques for Efficient Acceleration of Deep Neural Network Inference with Analog-AI (Invited).
Proceedings of the IEEE International Symposium on Circuits and Systems, 2021
Mushroom-Type phase change memory with projection liner: An array-level demonstration of conductance drift and noise mitigation.
Proceedings of the IEEE International Reliability Physics Symposium, 2021
2020
Proceedings of the IEEE International Symposium on Circuits and Systems, 2020
Neuromorphic Computing with Phase Change, Device Reliability, and Variability Challenges.
Proceedings of the 2020 IEEE International Reliability Physics Symposium, 2020
Proceedings of the 2nd IEEE International Conference on Artificial Intelligence Circuits and Systems, 2020
2019
AI hardware acceleration with analog memory: Microarchitectures for low energy at high speed.
IBM J. Res. Dev., 2019
Analog-to-Digital Conversion With Reconfigurable Function Mapping for Neural Networks Activation Function Acceleration.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2019
Proceedings of the 19th Non-Volatile Memory Technology Symposium, 2019
Proceedings of the IEEE International Reliability Physics Symposium, 2019
2018
Nat., 2018
2017
Toward on-chip acceleration of the backpropagation algorithm using nonvolatile memory.
IBM J. Res. Dev., 2017
Reducing circuit design complexity for neuromorphic machine learning systems based on Non-Volatile Memory arrays.
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Proceedings of the IEEE International Symposium on Circuits and Systems, 2017
Improved Deep Neural Network Hardware-Accelerators Based on Non-Volatile-Memory: The Local Gains Technique.
Proceedings of the IEEE International Conference on Rebooting Computing, 2017
2016
Circuit-Level Benchmarking of Access Devices for Resistive Nonvolatile Memory Arrays.
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
IEEE J. Emerg. Sel. Topics Circuits Syst., 2016
Accelerating machine learning with Non-Volatile Memory: Exploring device and circuit tradeoffs.
Proceedings of the IEEE International Conference on Rebooting Computing, 2016
Large-scale neural networks implemented with Non-Volatile Memory as the synaptic weight element: Impact of conductance response.
Proceedings of the 46th European Solid-State Device Research Conference, 2016
2015
Non-volatile memory as hardware synapse in neuromorphic computing: A first look at reliability issues.
Proceedings of the IEEE International Reliability Physics Symposium, 2015
2013
ACM J. Emerg. Technol. Comput. Syst., 2013
2008
IBM J. Res. Dev., 2008
2000
1998