Gensuke Goto

According to our database, Gensuke Goto authored at least 9 papers between 1988 and 2014.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of four.

2014

A 32-bit CPU with zero standby power and 1.5-clock sleep/2.5-clock wake-up achieved by utilizing a 180-nm C-axis aligned crystalline In-Ga-Zn oxide transistor.

Atsuo Isobe, Hikaru Tamura, Kiyoshi Kato, Takuro Ohmaru, Wataru Uesugi, Takahiko Ishizu, Tatsuya Onuki, Kazuaki Ohshima, Takanori Matsuzaki, Atsushi Hirose, Yasutaka Suzuki, Naoaki Tsutsui, Tomoaki Atsumi, Yutaka Shionoiri, Gensuke Goto, Jun Koyama, Masahiro Fujita, Shunpei Yamazaki

Proceedings of the Symposium on VLSI Circuits, 2014

Embedded SRAM and Cortex-M0 core with backup circuits using a 60-nm crystalline oxide semiconductor for power gating.

Hikaru Tamura, Kiyoshi Kato, Takahiko Ishizu, Tatsuya Onuki, Wataru Uesugi, Takuro Ohmaru, Kazuaki Ohshima, Hidetomo Kobayashi, Seiichi Yoneda, Atsuo Isobe, Naoaki Tsutsui, Suguru Hondo, Yasutaka Suzuki, Yutaka Okazaki, Tomoaki Atsumi, Yutaka Shionoiri, Yukio Maehashi, Gensuke Goto, Masahiro Fujita, James Myers, Pekka Korpinen, Jun Koyama, Yoshitaka Yamamoto, Shunpei Yamazaki

Proceedings of the 2014 IEEE Symposium on Low-Power and High-Speed Chips, 2014

2011

A middle-grain circuit partitioning strategy for 3-D integrated floating-point multipliers.

Jubee Tada, Ryusuke Egawa, Kazushige Kawai, Hiroaki Kobayashi, Gensuke Goto

Proceedings of the 2011 IEEE International 3D Systems Integration Conference (3DIC), Osaka, Japan, January 31, 2011

2009

Evaluation of fine grain 3-D integrated arithmetic units.

Ryusuke Egawa, Jubee Tada, Hiroaki Kobayashi, Gensuke Goto

Proceedings of the IEEE International Conference on 3D System Integration, 2009

1992

A 54*54-b regularly structured tree multiplier.

Gensuke Goto, Tomio Sato, Masao Nakajima, Takao Sukemura

IEEE J. Solid State Circuits, September, 1992

An 8.5-ns 112-b transmission gate adder with a conflict-free bypass circuit.

Tomio Sato, Masato Sakate, H. Okada, T. Sukemura, Gensuke Goto

IEEE J. Solid State Circuits, April, 1992

1991

A Regularly Structured 54-bit Modified-Wallace-Tree Multiplier.

Takao Sato, Masao Nakajima, Takao Sukemura, Gensuke Goto

Proceedings of the VLSI 91, 1991

1990

A 64-bit floating-point processing unit with a horizontal instruction code for parallel operations.

Akira Katsuno, Hiromasa Takahashi, Hajime Kubosawa, Tomio Sato, Atsuhiro Suga, Gensuke Goto

Proceedings of the 1990 IEEE International Conference on Computer Design: VLSI in Computers and Processors, 1990

1988

A wafer-scale 170000-gate FFT processor with built-in test circuits.

Koichi Yamashita, Akinori Kanasugi, Shinpei Hijiya, Gensuke Goto, Nobutake Matsumura, Takehide Shirato

IEEE J. Solid State Circuits, April, 1988