Gengjie Chen

Orcid: 0000-0001-6016-4742

According to our database1, Gengjie Chen authored at least 23 papers between 2015 and 2024.

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Bibliography

2024
AMF-Placer 2.0: Open-Source Timing-Driven Analytical Mixed-Size Placer for Large-Scale Heterogeneous FPGA.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., September, 2024

2022
Pin-Accessible Legalization for Mixed-Cell-Height Circuits.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2022

Effective and Efficient Detailed Routing with Adaptive Rip-up Scheme and Pin Access Refinement.
Proceedings of the GLSVLSI '22: Great Lakes Symposium on VLSI 2022, Irvine CA USA, June 6, 2022

2021
AMF-Placer: High-Performance Analytical Mixed-size Placer for FPGA.
Proceedings of the IEEE/ACM International Conference On Computer Aided Design, 2021

REST: Constructing Rectilinear Steiner Minimum Tree via Reinforcement Learning.
Proceedings of the 58th ACM/IEEE Design Automation Conference, 2021

TreeNet: Deep Point Cloud Embedding for Routing Tree Construction.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

Placement for Wafer-Scale Deep Learning Accelerator.
Proceedings of the ASPDAC '21: 26th Asia and South Pacific Design Automation Conference, 2021

2020
SALT: Provably Good Routing Topology by a Novel Steiner Shallow-Light Tree Algorithm.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

Dr. CU: Detailed Routing by Sparse Grid Graph and Minimum-Area-Captured Path Search.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2020

2019
Dr. CU 2.0: A Scalable Detailed Routing Framework with Correct-by-Construction Design Rule Satisfaction.
Proceedings of the International Conference on Computer-Aided Design, 2019

Dim Sum: Light Clock Tree by Small Diameter Sum.
Proceedings of the Design, Automation & Test in Europe Conference & Exhibition, 2019

FIT: Fill Insertion Considering Timing.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

MARCH: MAze Routing Under a Concurrent and Hierarchical Scheme for Buses.
Proceedings of the 56th Annual Design Automation Conference 2019, 2019

Detailed routing by sparse grid graph and minimum-area-captured path search.
Proceedings of the 24th Asia and South Pacific Design Automation Conference, 2019

2018
RippleFPGA: Routability-Driven Simultaneous Packing and Placement for Modern FPGAs.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2018

Routability-driven and fence-aware legalization for mixed-cell-height circuits.
Proceedings of the 55th Annual Design Automation Conference, 2018

A two-step search engine for large scale boolean matching under NP3 equivalence.
Proceedings of the 23rd Asia and South Pacific Design Automation Conference, 2018

2017
Clock-aware ultrascale FPGA placement with machine learning routability prediction: (Invited paper).
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

SALT: Provably good routing topology by a novel steiner shallow-light tree algorithm.
Proceedings of the 2017 IEEE/ACM International Conference on Computer-Aided Design, 2017

Minimizing Thermal Gradient and Pumping Power in 3D IC Liquid Cooling Network Design.
Proceedings of the 54th Annual Design Automation Conference, 2017

2016
RippleFPGA: a routability-driven placement for large-scale heterogeneous FPGAs.
Proceedings of the 35th International Conference on Computer-Aided Design, 2016

2015
Reproducible Evaluation of Pan-Tilt-Zoom Tracking.
CoRR, 2015

Reproducible evaluation of Pan-Tilt-Zoom tracking.
Proceedings of the 2015 IEEE International Conference on Image Processing, 2015


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