Gefu Xu

According to our database, Gefu Xu authored at least 8 papers between 2005 and 2007.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of three.

2007

Scan cell design for launch-on-shift delay tests with slow scan enable.

Gefu Xu, Adit D. Singh

IET Comput. Digit. Tech., 2007

Delay Test Scan Flip-Flop: DFT for High Coverage Delay Testing.

Gefu Xu, Adit D. Singh

Proceedings of the 20th International Conference on VLSI Design (VLSI Design 2007), 2007

Achieving high transition delay fault coverage with partial DTSFF scan chains.

Gefu Xu, Adit D. Singh

Proceedings of the 2007 IEEE International Test Conference, 2007

Flip-flop Selection to Maximize TDF Coverage with Partial Enhanced Scan.

Gefu Xu, Adit D. Singh

Proceedings of the 16th Asian Test Symposium, 2007

2006

Output Hazard-Free Transition Tests for Silicon Calibrated Scan Based Delay Testing.

Adit D. Singh, Gefu Xu

Proceedings of the 24th IEEE VLSI Test Symposium (VTS 2006), 30 April, 2006

Low Cost Launch-on-Shift Delay Test with Slow Scan Enable.

Gefu Xu, Adit D. Singh

Proceedings of the 11th European Test Symposium, 2006

2005

Low Voltage Test in Place of Fast Clock in DDSI Delay Test.

Haihua Yan, Gefu Xu, Adit D. Singh

Proceedings of the 6th International Symposium on Quality of Electronic Design (ISQED 2005), 2005

Delay Defect Characterization Using Low Voltage Test.

Haihua Yan, Adit D. Singh, Gefu Xu

Proceedings of the 14th Asian Test Symposium (ATS 2005), 2005