Geeta Patil

According to our database, Geeta Patil authored at least 7 papers between 2015 and 2024.

Collaborative distances:

• Dijkstra number of four.
• Erdős number of five.

2024

CAMP: a hierarchical cache architecture for multi-core mixed criticality processors.

Arun S. Nair, Geeta Patil, Archit Agarwal, Aboli Vijayan Pai, Biju K. Raveendran, Sasikumar Punnekkat

Int. J. Parallel Emergent Distributed Syst., May, 2024

2021

MOESIL: A Cache Coherency Protocol for Locked Mixed Criticality L1 Data Cache.

Arun S. Nair, Aboli Vijayan Pai, Biju K. Raveendran, Geeta Patil

Proceedings of the 25th IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications, 2021

2019

MOESIF: a MC/MP cache coherence protocol with improved bandwidth utilisation.

Geeta Patil, Neethu Bal Mallya, Biju K. Raveendran

Int. J. Embed. Syst., 2019

MEDIATOR - A Mixed Criticality Deadline Honored Arbiter for Multi-core Real-time Systems.

Arun S. Nair, Louella Mesquita Colaco, Geeta Patil, Biju K. Raveendran, Sasikumar Punnekkat

Proceedings of the 23rd IEEE/ACM International Symposium on Distributed Simulation and Real Time Applications DS-RT 2019, 2019

2017

DTLB: Deterministic TLB for Tightly Bound Hard Real-Time Systems.

Kajal Varma, Geeta Patil, Biju K. Raveendran

Proceedings of the 30th International Conference on VLSI Design and 16th International Conference on Embedded Systems, 2017

2015

Way Halted Prediction Cache: An Energy Efficient Cache Architecture for Embedded Processors.

Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran

Proceedings of the 28th International Conference on VLSI Design, 2015

Simulation based Performance Study of Cache Coherence Protocols.

Neethu Bal Mallya, Geeta Patil, Biju K. Raveendran

Proceedings of the IEEE International Symposium on Nanoelectronic and Information Systems, 2015