Gedeon Nyengele

Orcid: 0000-0002-5028-7252

According to our database1, Gedeon Nyengele authored at least 9 papers between 2016 and 2024.

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Bibliography

2024
Amber: A 16-nm System-on-Chip With a Coarse- Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
IEEE J. Solid State Circuits, March, 2024

Onyx: A 12nm 756 GOPS/W Coarse-Grained Reconfigurable Array for Accelerating Dense and Sparse Applications.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits 2024, 2024


2023
AHA: An Agile Approach to the Design of Coarse-Grained Reconfigurable Accelerators and Compilers.
ACM Trans. Embed. Comput. Syst., March, 2023

2022
Amber: A 367 GOPS, 538 GOPS/W 16nm SoC with a Coarse-Grained Reconfigurable Array for Flexible Acceleration of Dense Linear Algebra.
Proceedings of the IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits 2022), 2022


2020

2018
Optimized Gateway Placement for Interference Cancellation in Transmit-Only LPWA Networks.
Sensors, 2018

2016
Reliability and longer range for low power transmitters with on demand network MIMO.
Proceedings of the 2016 IEEE International Conference on RFID, 2016


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