Gayatri Mehta

Orcid: 0000-0001-7754-1874

According to our database1, Gayatri Mehta authored at least 34 papers between 2006 and 2024.

Collaborative distances:

Timeline

Legend:

Book 
In proceedings 
Article 
PhD thesis 
Dataset
Other 

Links

On csauthors.net:

Bibliography

2024
SecurityCloak: Protection against cache timing and speculative memory access attacks.
J. Syst. Archit., 2024

2023
A Low-Power Wireless System for Predicting Early Signs of Sudden Cardiac Arrest Incorporating an Optimized CNN Model Implemented on NVIDIA Jetson.
Sensors, February, 2023

Guard Cache: Creating Noisy Side-Channels.
IEEE Comput. Archit. Lett., 2023

Guard Cache: Creating False Cache Hits and Misses To Mitigate Side-Channel Attacks.
Proceedings of the Silicon Valley Cybersecurity Conference, 2023

Streaming Sparse Data on Architectures with Vector Extensions using Near Data Processing.
Proceedings of the International Symposium on Memory Systems, 2023

Performance Implications of Async Memcpy and UVM: A Tale of Two Data Transfer Modes.
Proceedings of the IEEE International Symposium on Workload Characterization, 2023

NextGen-Malloc: Giving Memory Allocator Its Own Room in the House.
Proceedings of the 19th Workshop on Hot Topics in Operating Systems, 2023

2022
A Low-power Dry Electrode-based ECG Signal Acquisition with De-noising and Feature Extraction.
J. Signal Process. Syst., 2022

Memory-Side Acceleration and Sparse Compression for Quantized Packed Convolutions.
Proceedings of the 2022 IEEE 34th International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), 2022

HETEROGENEOUS ARCHITECTURE FOR SPARSE DATA PROCESSING.
Proceedings of the IEEE International Parallel and Distributed Processing Symposium, 2022

Sparse-T: Hardware Accelerator Thread for Unstructured Sparse Data Processing.
Proceedings of the 41st IEEE/ACM International Conference on Computer-Aided Design, 2022

2020
CHASM: Security Evaluation of Cache Mapping Schemes.
Proceedings of the Embedded Computer Systems: Architectures, Modeling, and Simulation, 2020

A Dry Electrode-Based ECG Sensor with Motion Artifacts Cancellation and Signal Analysis for Heart Irregularity Detection.
Proceedings of the 2020 IEEE Sensors, Rotterdam, The Netherlands, October 25-28, 2020, 2020

AMOEBA: a coarse grained reconfigurable architecture for dynamic GPU scaling.
Proceedings of the ICS '20: 2020 International Conference on Supercomputing, 2020

2015
Crowdsourcing the mapping problem for design space exploration of custom reconfigurable architecture designs.
Hum. Comput., 2015

Characterizing rate distortion region for video coding from first principles.
Proceedings of the 49th Annual Conference on Information Sciences and Systems, 2015

2014
Fundamental Limits of Video Coding: A Closed-form Characterization of Rate Distortion Region from First Principles.
CoRR, 2014

SmartBricks: A Visual Environment to Design and Explore Novel Custom Domain-Specific Architectures.
Proceedings of the 2014 IEEE International Parallel & Distributed Processing Symposium Workshops, 2014

2013
UNTANGLED: A Game Environment for Discovery of Creative Mapping Strategies.
ACM Trans. Reconfigurable Technol. Syst., 2013

Data-Driven Mapping Using Local Patterns.
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst., 2013

Implementation and validation of architectural space exploration techniques for domain-specific reconfigurable computing.
Des. Autom. Embed. Syst., 2013

UNTANGLED - An interactive mapping game for engineering education.
Proceedings of the 2013 IEEE International Conference on Microelectronic Systems Education, 2013

Cross-Architectural Study of Custom Reconfigurable Devices Using Crowdsourcing.
Proceedings of the 2013 IEEE International Symposium on Parallel & Distributed Processing, 2013

2012
Guest Editor's Note - Interaction between Compilers and Computer Architectures.
J. Circuits Syst. Comput., 2012

2010
An architectural space exploration tool for domain specific reconfigurable computing.
Proceedings of the 24th IEEE International Symposium on Parallel and Distributed Processing, 2010

Power, performance and security optimized hardware design for H.264.
Proceedings of the 6th Cyber Security and Information Intelligence Research Workshop, 2010

2009
Interconnect customization for a hardware fabric.
ACM Trans. Design Autom. Electr. Syst., 2009

2008
Reducing energy by exploring heterogeneity in a coarse-grain fabric.
Proceedings of the 22nd IEEE International Symposium on Parallel and Distributed Processing, 2008

2007
Interconnect Customization for a Coarse-grained Reconfigurable Fabric.
Proceedings of the 21th International Parallel and Distributed Processing Symposium (IPDPS 2007), 2007

2006
Reducing power while increasing performance with supercisc.
ACM Trans. Embed. Comput. Syst., 2006

A VLIW Processor With Hardware Functions: Increasing Performance While Reducing Power.
IEEE Trans. Circuits Syst. II Express Briefs, 2006

A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture.
J. Low Power Electron., 2006

Design space exploration for low-power reconfigurable fabrics.
Proceedings of the 20th International Parallel and Distributed Processing Symposium (IPDPS 2006), 2006

A Low-Energy Reconfigurable Fabric for the SuperCISC Architecture.
Proceedings of the 14th IEEE Symposium on Field-Programmable Custom Computing Machines (FCCM 2006), 2006


  Loading...