Gayathri Chalivendra

According to our database, Gayathri Chalivendra authored at least 2 papers between 2010 and 2011.

Collaborative distances:

• Dijkstra number of five.
• Erdős number of four.

2011

A new balanced 4-moduli set {2<i>^k</i>, 2<i>ⁿ</i> - 1, 2<i>ⁿ</i> + 1, 2<i>ⁿ⁺¹</i>-1} and its reverse converter design for efficient fir filter implementation.

Gayathri Chalivendra, Vinay Hanumaiah, Sarma B. K. Vrudhula

Proceedings of the 21st ACM Great Lakes Symposium on VLSI 2010, 2011

2010

A Low Power, High Performance Threshold Logic-Based Standard Cell Multiplier in 65 nm CMOS.

Samuel Leshner, Krzysztof S. Berezowski, Xiaoyin Yao, Gayathri Chalivendra, Saurabh Patel, Sarma B. K. Vrudhula

Proceedings of the IEEE Computer Society Annual Symposium on VLSI, 2010